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Memory ordering
Memory Consistency
Memory Ordering: a Value-Based Approach
Connect User Guide Armv8-A Memory Systems
Recent Advances in Memory Consistency Models for Hardware
Fence Scoping
Fences in Weak Memory Models
Linux-Kernel Memory Ordering: Help Arrives at Last!
The Semantics of X86-CC Multiprocessor Machine Code
Memory Ordering in Modern Microprocessors Paul E
Itanium Processor Microarchitecture
Weak Memory Models with Matching Axiomatic and Operational Definitions
Louvre: Lightweight Ordering Using Versioning for Release Consistency
A Better X86 Memory Model: X86-TSO
Memory Consistency
Scalable Correct Memory Ordering Via Relativistic Programming
Linux-Kernel Memory Ordering: Help Arrives at Last!
Memory Consistency Models of Modern Cpus
Introduction to the MIPS64® Architecture Comes As Part of a Multi-Volume Set
Top View
Concurrency in the Linux Kernel
Futex Based Locks for C11's Generic Atomics
Memory Barriers in Linux Kernel
C++11: the Dawn of New Standards (And a Preview of Upcoming Transactional Memory TS)
The Linux Memory Model
P0098R0: Towards Implementation and Use of Memory Order Consume
Relaxed Memory Models Must Be Rigorous
Memory Ordering in Modern Microprocessors, Part I
Memory Barriers in the Linux Kernel Semantics and Practices
A Primer on Memory Consistency and CACHE COHERENCE CONSISTENCY on MEMORY a PRIMER and Cache Coherence Consistency and Daniel J
Fortran Code Modernization
Software Implications of High-Performance Memory Systems
Imposing Minimal Memory Ordering on Multiprocessors
Memory Models: a Case for Rethinking Parallel Languages and Hardware
Introduction to the MIPS32 Architecture
C++ Memory Model Valentin Ziegler Fabio Fracassi Meeting C++ Berlin, December 6Th, 2014 the Machine Does Not Execute the Code You Wrote…
INVISIFENCE: Performance-Transparent Memory Ordering in Conventional Multiprocessors
Reordering Constraints for Pthread-Style Locks