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This method is utilized as a gate drive and approach to design high−performance bootstrap gate drive accompanying bias circuit, both referenced to the source of circuits for high−frequency, high−power, and the main switching device. Both the driver and bias circuit high−efficiency switching applications using a power swing between the two input voltage rails together with the MOSFET and IGBT. It should be of interest to power source of the device. However, the driver and its floating electronics engineers at all levels of experience. In the most bias can be implemented by low−voltage circuit elements of switching applications, efficiency focuses on switching since the input voltage is never applied across their losses that are mainly dependent on switching speed. components. The driver and the ground referenced control Therefore, the switching characteristics are very important signal are linked by a level shift circuit that must tolerate the in most of the high−power switching applications presented high−voltage difference and considerable capacitive in this paper. One of the most widely used methods to supply switching currents between the floating high−side and power to the high−side gate drive circuitry of the ground−referenced low−side circuits. The high−voltage high−voltage gate−drive IC is the bootstrap power supply. gate−drive ICs are differentiated by unique level−shift This bootstrap power supply technique has the advantage of design. To maintain high efficiency and manageable power being simple and low cost. However, it has some limitations, dissipation, the level−shifters should not draw any current on time of duty−cycle is limited by the requirement to during the on−time of the main switch. A widely used refresh the charge in the bootstrap capacitor and serious technique for these applications is called pulsed latch level problems occur when the negative voltage is presented at the translators, shown in Figure 1. source of the switching device. The most popular bootstrap circuit solutions are analyzed; including the effects of Bootstrap Drive Circuit Operation parasitic elements, the bootstrap resistor, and capacitor; on The bootstrap circuit is useful in a high−voltage gate the charge of the floating supply application. driver and operates as follows. When the VS goes below the IC supply voltage VDD or is pulled down to ground (the HIGH−SPEED GATE−DRIVER CIRCUITRY low−side switch is turned on and the high−side switch is turned off), the bootstrap capacitor, CBOOT, charges through Bootstrap Gate−Drive Technique the bootstrap resistor, RBOOT, and bootstrap diode, DBOOT, The focus of this topic is the bootstrap gate−drive circuit from the VDD power supply, as shown in Figure 2. This is requirements of the power MOSFET and IGBT in various provided by VBS when VS is pulled to a higher voltage by the switching−mode power−conversion applications. Where high−side switch, the VBS supply floats and the bootstrap input voltage levels prohibit the use of direct−gate drive diode reverses bias and blocks the rail voltage (the low−side circuits for high−side N−channel power MOSFET or IGBT, switch is turned off and high−side switch is turned on) from the principle of bootstrap gate−drive technique can be the IC supply voltage, VDD. VB UVLO PULSE GENERATOR IN HO R through NOISE R − CANCELLER S Q gate driver Shoot current compensated VS Figure 1. Level−Shifter in High−Side Drive IC © Semiconductor Components Industries, LLC, 2017 1 Publication Order Number: August, 2021 − Rev. 3 AND9674/D AND9674/D R D BOOT BOOT DC SUPPLY HIN t VB RG1 VDD HO Q1 ILOAD VS −COM CBOOT DD V V S t LOAD Q2 RG2 −VS Freewheeling COM LO Figure 4. VS Waveforms During Turn−off Bootstrap charge current path Cause of Negative Voltage on VS Pin Bootstrap discharge current path A well−known event that triggers VS go below COM (ground) is the forward biasing of the low−side freewheeling Figure 2. Bootstrap Power Supply Circuit diode, as shown in Figure 5. Drawback of Bootstrap Circuitry Major issues may appear during commutation, just before The bootstrap circuit has the advantage of being simple the freewheeling diode starts clamping. and low cost, but has some limitations. In this case, the inductive parasitic elements, LS1 and Duty−cycle and on time is limited by the requirement to LS2, may push VS below COM, more than as described above or normal steady−state condition. refresh the charge in the bootstrap capacitor, CBOOT. The biggest difficulty with this circuit is that the negative The amplitude of negative voltage is proportional to the voltage present at the source of the switching device during parasitic inductances and the turn−off speed, di/dt, of the turn−off causes load current to suddenly flow in the switching device; as determined by the gate drive resistor, low−side freewheeling diode, as shown in Figure 3. RGATE, and input capacitance, Ciss, of switching device. This negative voltage can be trouble for the gate driver’s It is sum of Cgs and Cgd, called Miller capacitance. output stage because it directly affects the source VS pin of VCC the driver or PWM control IC and might pull some of the DBOOT internal circuitry significantly below ground, as shown in Figure 4. The other problem caused by the negative voltage VDC IN HVIC VB transient is the possibility to develop an over−voltage INPUT condition across the bootstrap capacitor. CBOOT Q1 A B The bootstrap capacitor, CBOOT, is peak charged by the VDD HO RGATE bootstrap diode, DBOOT, from VDD the power source. LS1 iLOAD C GND Since the VDD power source is referenced to ground, the VS C C DRV V maximum voltage that can build on the bootstrap capacitor GND LS2 iFree OUT −V COUT is the sum of VDD and the amplitude of the negative voltage S D1 at the source terminal. DC SUPPLY Figure 5. Step−Down Converter Applications RBOOT DBOOT VB RG1 VDD HO Q1 High Side OFF HIN HIN iLoad Ls1 BOOT LIN LIN VS C ifree C Ls2 IN RG2 COM LO Q2 Freewheeling Path Figure 3. Half−Bridge Application Circuits www.onsemi.com 2 AND9674/D Figure 6 shows the waveforms of the high−side, shifter of the high−side gate driver suffers form a lack of the N−channel MOSFET during turn−off. operation voltage headroom. This should be noted, but proves trivial in most applications, as the high−side in not usually required to change state immediately following a switching event. A−Point VBS VDC + VGS, Miller B−Point INPUT C−Point VDC Recovery Time OUTPUT VGS = B−C Point Figure 8. Waveforms in Case of Signal Missing Figure 6. Waveforms During Turn−off Consideration of Latch−up Problem Effects in the Undershoot Spike on VS Pin If undershoot exceeds the absolute maximum rating The most integrated high−voltage gate−drive ICs have specified in the datasheet, the gate drive IC suffers damage parasitic diodes, which, in forward or reverse break−down, or the high−side output is temporarily unresponsive to input may cause parasitic SCR latch−up.