Transistor Technologies for High Efficiency and Linearity HEMT Requirements for Transistors in Power Amplifiers High microwave gain Iout Low on-resistance & low “knee voltage” FET High power density High voltage capability Linearity Vout Vmin Nonlinear Ease of matching Iout Ease of biasing HBT Adequate heatsinking Low cost (high yield) Reliability & ruggedness Vout Stability Vmin Nonlinear Central Concern for Transistors in ECE265C What is highest voltage that can be maintained? What is highest current that can be delivered? What is highest power that can be withstood? Safe Operating Area for Transistors I On-state breakdown Imax voltage Maximum power dissipation Off-state breakdown voltage V Imax depends on device size Maximum power dissipation depends on size and duty cycle - worse for CW tone than for high PAR signals Tradeoff of Breakdown Voltage and ft To avoid breakdown, generally must limit peak electric field to below a critical value, Eb To achieve high voltage, one can design the high field region to be long: Vbk= Eb *wc The large wc tends to increase transit time for carriers, resulting in low ft: Ttr>wc/vsat, Ft=1/(2p Ttr) The product of Vbk and ft tends to be independent of wc: Vbk*ft <= Eb * vsat / 2 p CMOS scaling through Moore’s Law acts to drive up ft, but it drives down Vbk at the same time. Speed-Voltage Tradeoff in Transistors Channel or BC Source or base Drain or collector depletion region Ttr Wc Ft=1/(2pTtr) E breakdown Ttr=Wc/vsat (or ½ Wc/vsat) b: electric field BV=1/2 Eb Wc (or Eb Wc) BV*ft = ½ Eb Wc * 1/2p vsat /Wc Johnson Figure-of-merit BV*ft ~ 1/2p Eb *vsat Transistor Size Need to pick device large enough to support Imax Not necessarily well described in SPICE models For bipolars: Ic/Aemitter = Jc < 2-5 mA/um2 for Si < 0.5 mA/um2 for GaAs For FETs: Id/ Wg < 0.3-0.8 A/mm for CMOS 0.1 A/mm for LDMOS 0.2-1 A/mm for pHEMT 0.5-1.5 A/mm for GaN Thermal Effects in Power Transistors •Burnout (melting of portions of device, rapid diffusion of defects, excess stress, etc) •Degradation •Thermal runaway in bipolar transistors •Decreased performance: reduced Iout, lower ft, etc •Thermally induced distortion & memory effect •Difference between cw and short-time ac characteristics Negative Output Conductance due to heating Basics of Thermal Circuits Thermal Resistance of Transistor Main contribution is often Rth to back of chip K(W/cmK) 0.003 Teflon 0.015 SiO2 0.45 GaAs 0.75 InP 1.3 GaN 1.5 Silicon 3.2 Gold 3.8 Copper 4.4 SiC 20 Diamond 0 2 4 6 8 10 12 14 16 18 20 Thermal Resistance Calculations Using 3D Structure Simulators (solve Laplace’s equation) InP HBT CMOS SOI Ansys, comsol, sentaurus, etc Thermal Resistance Estimate 1 Rth for section near device is >> Rth at bottom Thermal Resistance Estimate 2 How To Decrease Thermal Resistance Thin substrates Thermal Vias Heat Spreaders Flip-chip bonding (? sometimes) FETs for Power Amplifiers Si CMOS LDMOS (Laterally Diffused MOS) GaAs MESFET InP HEMT GaN pHEMT Different Flavors of FET MOSFET MESFET HEMT Limits in CMOS Transistors •Limits on Ids: maximum channel charge is limited by gate oxide field: qNsmax~ eox Eoxmax •Oxide breakdown: typically occurs at 10MV/cm=> 1V for every 10A of gate oxide Gate-channel breakdown will occur at source or drain, wherever field is highest. There are slow oxide “breakdown” mechanisms too (time- dependent dielectric breakdown) •Avalanche breakdown in channel at high VDS values •Oxide charging: when operated at high Vds, electrons are injected into the gate oxide, creating trapped charge which shifts device threshold (hot carrier injection) Hot Electron Generation High Voltage Breakdown Mechanism of MOS Transistor Impact ionization at drain edge of gate Source Channel Drain - + - - Moderate electric field High electric field What happens to holes generated by impact ionization? They flow to the substrate and to the source. They cause some extra current due to body effect. They can be measured as substrate or well current. CMOS Id-Vds curve (generic) 2.5 2.0 1.5 ID.i, A ID.i, 1.0 0.5 0.0 0.0 0.5 1.0 1.5 2.0 2.5 3.0 Vds SOI effects Gate Source Drain N+ p N+ "snapback" Bipolar Impact ionization injection current Parasitic bipolar transistor Fed by impact ionization Causes excess Id, lower BV Lightly Doped Drain Structure (LDD) To Minimize Hot Electron Effects Minimize electric field near drain Technique to improve CMOS PAs: Differential Topology • Double the available voltage swing • Even-order harmonic suppression • Double the frequency of current injection into substrate – Reduce the potential for LO-pulling • The tail current source is removed from the standard differential pair (this is a “quasi-differential” structure) – DC current set by the biasing of input devices – Max. current set by the input voltage swing • May require differential to single-ended output conversion (balun) Technique to improve CMOS PAs: Cascode Structure • Generally used in Op-Amps and other analog designs – Increase the small-signal output resistance – Reduce the Miller effect • In the case of RF PA, isolate the input and output nodes – Reduce the impact of oxide breakdown • On the cascode device, – Vox(max) = Vout(max) - Vbias • On the bottom device, – Vox(max) = Vcasc - Vin = Vbias - Vt - Vin(min) Id-Vds Characteristics of Cascode 300mA Id-Vds for Cascode: Higher Ron 200mA Lower Idmax Body effect on top FET 100mA Higher Vmin decreases efficiency 0A 0V 0.5V 1.0V 1.5V 2.0V 2.5V ID(m2) ID(m4) vdd1 Stacked-FET Structure Vds and Vgs swing of each FET 4.0 3.5 3.0 Vds, i 2.5 2.0 Vds3 Vgs3 Vds2 Vgs2 Vds1, V Vds1, Vgs1, V Vgs1, 1.5 1.0 Vgs, i 0.5 0.0 0.0 0.2 0.4 0.6 0.8 1.0 time, nsec • All FETs are operating in the safe region Stacked-FET Structure Vds and Vgs swing of each FET 4.0 3.5 3.0 Vds, i 2.5 2.0 Vds3 Vgs3 Vds2 Vgs2 Vds1, V Vds1, Vgs1, V Vgs1, 1.5 1.0 Vgs, i 0.5 0.0 0.0 0.2 0.4 0.6 0.8 1.0 time, nsec • All FETs are operating in the safe region Stacked-FET Structure 2 3Ropt Zs2 C3 Zs3= 2Ropt C2 Z = R s2 opt Id~gm Vgs ~gm Vt C2/(C2+Cgs) C Tailor swing at each drain gs 1 Z @ 1 + and gate by proper s 2 C g selection of gate capacitor 2 m Stacked FET Approach for CMOS PAs Works well at least up to 90GHz !!! 10 5 0 -5 -10 parameters (dB) parameters - -15 S -20 75 80 85 90 95 100 105 110 Freq (GHz) 50 mW Psat at 90GHz In 45 nm CMOS SOI Jefy Jayamon (UCSD) Power Combining with Distributed Active Transformers Aoki, Kee, Hajimiri and Rutledge (Caltech) CMOS Amplifier with On-Chip Transformer Grain of salt LDMOS LDMOS Wsi / Poly Gate Drain Source Metal N+ PHV NHV N+ P+ Enhancement P-epi Lightly doped P+ Sinker n - type LDMOS Model: Approach 1 D. Klassen et al LDMOS Transistors are current workhorses for Basestation PAs LDMOS prices Historically $1 / peak Watt (Basestation PA 200W peak)=> $200 With present heavy competition $ 0.5 / peak Watt GaAs MESFET GaAs-based Metal-Schottky FET Low Ron, high ft, high BV High gm compared with Si Microwave IC capability (S-I substrate) Typically depletion-mode (negative supply needed) gm varies with Vin gm Rout moderate, varies with f and Vds Gate conducts at high bias rectifies input signal Vgs Vt Vgon Id Vds Channel Charge in GaAs MESFETs X=w If reverse bias on Schottky gate is increased, Channel becomes more depleted, channel charge decreases Channel charge Q ~ q Nd (a-w) w=sqrt[2e(V+Vbi)/qNd] Q => I-V curves similar to MOSFET Gradual Channel Approx. 2 Id=1/2 CinmW/L(Vgs-Vt) in saturation region Vgs Typically depletion mode Vt Vbi DC vs Pulsed Id-Vds Characteristics of GaAs FET Idealized Current Transient for III-V FET How To Increase Breakdown Voltage in III-V FETs Multiple gate recesses particularly on drain side Just like "drain extension" MOSFET Field plate Modulates electric field at drain edge of gate Just like LDMOS HEMT GaAs-based High Electron Mobility FET Low Ron, high ft, high BV Very high gm Microwave IC capability (S-I substrate) Typically depletion-mode (negative supply needed) gm varies only slightly with Vin gm Rout high, can be controlled Gate conducts at high bias rectifies input signal Vgs Id Vds HEMT MOSFET GaAs Pseudomorphic HEMT (pHEMT) Ultrahigh Speed Transistors •Gate length 25 nm •InGaAs channel with 70% In on InP substrate Applications of E-pHEMT Technology for Cellular Handset Power Amplifiers Normalized to 1 mm Gate Width Shyh-Liang Fu, Pin-Fan Chen, Harry Yu, and Dave Wu Wireless Semiconductor Division 0.4 Agilent Technologies, San Jose, CA 0.3 Load-Pull for PAE Tuning 0.2 30 80 Ids (A) 70 0.1 25 60 0 50 (%)PAE 0 1 2 3 4 5 Gain_PAE tuning Vds (V) 20 40 Gain (dB) Gain PAE_PAE tuning 30 Normalized to 1 mm Gate Width 15 20 0.7 10 0.6 10 0 0.5 -5 0 5 10 15 20 25 0.4 Pout (dBm) 0.3 Gm (S) Gm 0.2 0.1 0 0.2 0.4 0.6 0.8 1 1.2 Vgs (V) Heterojunction Bipolar Transistors HBT Heterojunction Bipolar Transistor Pros High microwave gain High power density =small die size Straightforward fabrication (simple lithography no Vth control problems) Single power supply High efficiency Good linearity Thermal issues Cons (including thermal runaway) Finite base current Saturation charge storage GaAs HBT Power Amplifier Example WCDMA Examples of Bipolar Transistor Breakdown Characteristics To maximize breakdown voltage in bipolar transistors: When using common emitter configuration Drive base with a low impedance source not a current source Or Use common base configuration Or Use cascode connection Gain vs Frequency Common emitter Common base Bias Circuit Considerations Do not want to short out RF input signal Want temperature independent bias Often use current mirror Use smaller device to set bias, to conserve