Cell Broadband Engine Architecture Version 1.01 October 3, 2006 ® Copyright and Disclaimer © Copyright International Business Machines Corporation, Sony Computer Entertainment Incorporated, Toshiba Corporation 2005, 2006 All Rights Reserved Printed in the United States of America October 2006 The following are registered trademarks of International Business Machines Corporation in the United States, or other countries, or both. IBM PowerPC IBM Logo PowerPC Architecture ibm.com Cell Broadband Engine is a trademark of Sony Computer Entertainment, Inc. Other company, product, and service names may be trademarks or service marks of others. All information contained in this document is subject to change without notice. The products described in this document are NOT intended for use in applications such as implantation, life support, or other hazardous uses where malfunction could result in death, bodily injury, or catastrophic property damage. The information contained in this document does not affect or change IBM product specifications or warranties. Nothing in this document shall operate as an express or implied license or indemnity under the intellectual property rights of IBM or third parties. All information contained in this docu- ment was obtained in specific environments, and is presented as an illustration. The results obtained in other operating environments can vary. THE INFORMATION CONTAINED IN THIS DOCUMENT IS PROVIDED ON AN “AS IS” BASIS. In no event will IBM be liable for damages arising directly or indirectly from any use of the information contained in this document. IBM Systems and Technology Group 2070 Route 52, Bldg. 330 Hopewell Junction, NY 12533-6351 The IBM home page can be found at ibm.com The IBM semiconductor solutions home page can be found at ibm.com/chips October 3, 2006 Version 1.01 Cell Broadband Engine Architecture Contents List of Figures ............................................................................................................... 11 List of Tables ................................................................................................................. 13 Preface ........................................................................................................................... 15 Who Should Read This Manual ............................................................................................................ 15 Document Organization ........................................................................................................................ 15 Related Publications ............................................................................................................................. 16 Conventions and Notation ..................................................................................................................... 17 References to Registers, Fields, and Bits ............................................................................................. 18 Endian Order ......................................................................................................................................... 18 Revision Log ................................................................................................................. 19 1. Introduction to Cell Broadband Engine Architecture ............................................ 23 1.1 Organization of a CBEA-Compliant Processor ............................................................................... 23 1.1.1 PowerPC Processor Element ................................................................................................ 25 1.1.2 Synergistic Processor Unit .................................................................................................... 25 1.1.3 Memory Flow Controller ........................................................................................................ 25 1.1.4 Internal Interrupt Controller .................................................................................................... 26 1.2 Storage Types ................................................................................................................................. 26 1.2.1 Local Storage Addressing ..................................................................................................... 26 1.2.2 Main Storage Addressing ...................................................................................................... 27 1.2.3 Main Storage Attributes ......................................................................................................... 27 1.3 Cache Replacement Management Facility ..................................................................................... 28 1.4 Instructions, Commands, and Facilities .......................................................................................... 28 1.5 Reserved Fields and Registers ....................................................................................................... 28 1.6 Implementation-Dependent Fields and Registers ........................................................................... 29 User Mode Environment ............................................................................31 2. Overview .................................................................................................................... 32 2.1 Instruction and Command Classes ................................................................................................. 32 2.1.1 Defined Class ........................................................................................................................ 32 2.1.2 Illegal Class .......................................................................................................................... 33 2.1.3 Reserved Class ..................................................................................................................... 33 2.2 Forms of Defined Instructions and Commands ............................................................................... 33 2.2.1 Preferred Forms .................................................................................................................... 33 2.2.2 Invalid Forms ......................................................................................................................... 34 2.2.3 Optional Forms ...................................................................................................................... 34 2.2.4 Optional Fields ....................................................................................................................... 34 2.3 Exceptions ....................................................................................................................................... 34 2.4 SPU Events ..................................................................................................................................... 35 3. Storage Models ......................................................................................................... 37 3.1 Virtual Storage Model ...................................................................................................................... 37 3.2 SPU Local Storage Model ............................................................................................................... 37 3.2.1 Local Storage Access ............................................................................................................ 38 3.2.1.1 Mapping Requirements .................................................................................................. 38 3.2.1.2 Local Storage Access Exceptions .................................................................................. 38 Version 1.01 Contents October 3, 2006 Page 3 of 352 Cell Broadband Engine Architecture 3.3 Single-Copy Atomicity ..................................................................................................................... 38 3.4 Cache Models ................................................................................................................................. 39 3.5 Memory Coherence ......................................................................................................................... 40 3.6 Storage Control Attributes ............................................................................................................... 40 3.7 Shared Storage ............................................................................................................................... 41 4. PowerPC Processor Element ................................................................................... 43 4.1 PowerPC Architecture, Book I and Book II Compatibility ................................................................ 43 4.1.1 Optional Features in PowerPC Architecture, Book I (Required for CBEA) ............................ 43 4.1.2 Incompatibilities with PowerPC Architecture, Book I ............................................................. 43 4.1.3 Optional Features in PowerPC Architecture, Book II (Required for CBEA) ........................... 44 4.1.4 Incompatibilities with PowerPC Architecture, Book II ............................................................ 44 4.1.5 Extensions to the PowerPC Architecture, Books I and II ....................................................... 44 5. Synergistic Processor Unit ....................................................................................... 45 6. Memory Flow Controller ..........................................................................................