MIPS R10000 Microprocessor User’s Manual Version 2.0 Copyright © 1996 MIPS Technologies, Inc. ALL RIGHTS RESERVED U.S. GOVERNMENT RESTRICTED RIGHTS LEGEND Use, duplication or disclosure by the Government is subject to restrictions as set forth in FAR 52.227.19(c)(2) or subparagraph (c)(1)(ii) of the Rights in Technical Data and Computer Software clause at DFARS 252.227-7013 and/or in similar or successor clauses in the FAR, or the DOD or NASA FAR Supplement. Contractor/manufacturer is Silicon Graphics, Inc., 2011 N. Shoreline Blvd., Mountain View, CA 94039-7311. RISCompiler, RISC/os, R2000, R6000, R4000, R4400, and R10000 are trademarks of MIPS Technologies, Inc. MIPS and R3000 are registered trademarks of MIPS Technologies, Inc. UNIX is a registered trademark in the United States and other countries, licensed exclusively through X/Open Company, Ltd. MIPS Technologies, Inc. 2011 North Shoreline Mountain View, California 94039-7311 http://www.mips.com Acknowledgments This book represents a consortium of efforts, and is principally derived from material provided by Randy Martin, Yung-Chin Chen, and Ken Yeager. Thanks also to Randy for his many painstaking reviews of this manual. Also providing invaluable service were the following: Shabbir Latif, for once again running point between Engineering and Publications, answering questions, and presenting tutorials to clarify the complicated details of the R10000 processor operations. Charlie Price, for use of his rejuvenated MIPS-4 Instruction Set Architecture. Steve Proffitt, for both his technical assistance, and helping handle the multitude of niggling details involved in getting this manual printed. The following also provided technical help in innumerable ways: Arun Mehta, Tim Layman, Greg Shippen, Yeffi Van Atta, John Brennan, Len Widra, Roy Johnson, Hector Sucar, Hong-Men Su, Mazin Khurshid, Steve Whitney, Doug Yanagawa (chip illustrations and socket pinouts), Mike Gupta, Steven Peltier, Rob Conrad, Hai Nguyen, Bill Voegtli, and Sharad Mehrotra at the University of Illinois. Remediating a prior deficiency, thanks to Tom McReynolds. In Production and Creative, thanks to Melissa Miller for her design of the cover (appreciable in hardcopy only, right now!); Yen Nguyen, for handling the printing; both Kay Maitz and Beth Fraker for resolving various design issues; and Michael Ritchie for tracking progress. Joe Heinrich December, 1995 Mt. View, California R10000 Microprocessor User's Manual Version 2.0 of October 10, 1996 iii R10000 Microprocessor User's Manual Version 2.0 of October 10, 1996 iv About This Manual This manual describes the MIPS R10000 RISC microprocessor (also referred to as the processor in this book). Glossary Certain specialized terms used in this book are defined in the Glossary at the end of this manual. Stylistic Conventions A brief note on some of the stylistic conventions used in this book: bits, fields, and registers of interest from a software perspective are italicized (such as the BE bit in the Config register). Signal names of more importance from a hardware point of view are rendered in bold (such as Reset*). The asterisk appended to the signal name (as in Reset*) indicates the signal is low-active. A range of bits uses a colon as a separator; for instance, (15:0) represents the 16-bit range that runs from bit 0, inclusive, through bit 15. In some places an ellipsis (15...0) or partial ellipsis (15..0) may used in place of a colon for visibility. Unfamiliar terms presented for the first time are printed in bold letters, and are followed as closely as possible by a definition or description. Errata This document is updated from changes made to the Version 1.0 document, dated June 26, 1995. Any corrections made to this manual will be found in the R10000 User Manual Errata for Revision 2.0. The errata in this manual are indicated by the following paragraph heading: Errata Specific changes to the text are underlined in the text, as shown below, while descriptions of changes that have been made are italicized, as shown below. PLLDis and SelDVCO signal descriptions are revised in Table 3-4. System designers must take care, especially in desktop applications, to ensure sufficient airflow. MIPS R10000 Microprocessor User's Manual Version 2.0 of October 10, 1996 v vi Getting MIPS Documents On-Line The information in this manual, and other MIPS-related product information, is also available over the Word Wide Web at: http://www.mips.com Requests can also be e-mailed to [email protected]. Version 2.0 of October 10, 1996 MIPS R10000 Microprocessor User's Manual Table of Contents vii Contents Acknowledgments About This Manual Glossary ..........................................................................................................................................v Stylistic Conventions ....................................................................................................................v Errata ...............................................................................................................................................v Getting MIPS Documents On-Line .............................................................................................vi MIPS R10000 Microprocessor User's Manual Version 2.0 of October 10, 1996 viii Table of Contents 1 Introduction to the R10000 Processor MIPS Instruction Set Architecture (ISA) .....................................................................................2 What is a Superscalar Processor?.................................................................................................3 Pipeline and Superpipeline Architecture..........................................................................3 Superscalar Architecture .....................................................................................................3 What is an R10000 Microprocessor? ............................................................................................4 R10000 Superscalar Pipeline ...............................................................................................5 Instruction Queues...............................................................................................................6 Execution Pipelines ..............................................................................................................6 64-bit Integer ALU Pipeline......................................................................................6 Load/Store Pipeline...................................................................................................7 64-bit Floating-Point Pipeline...................................................................................7 Functional Units ...................................................................................................................9 Primary Instruction Cache (I-cache)..................................................................................9 Primary Data Cache (D-cache) ...........................................................................................9 Instruction Decode And Rename Unit..............................................................................10 Branch Unit ...........................................................................................................................10 External Interfaces................................................................................................................10 Instruction Queues.........................................................................................................................11 Integer Queue .......................................................................................................................11 Floating-Point Queue...........................................................................................................11 Address Queue .....................................................................................................................12 Program Order and Dependencies ..............................................................................................13 Instruction Dependencies....................................................................................................13 Execution Order and Stalling .............................................................................................13 Branch Prediction and Speculative Execution .................................................................14 Resolving Operand Dependencies.....................................................................................14 Resolving Exception Dependencies...................................................................................15 Strong Ordering....................................................................................................................15 An Example of Strong Ordering ..............................................................................16 R10000 Pipelines .............................................................................................................................17 Stage 1 ....................................................................................................................................17 Stage 2 ....................................................................................................................................17 Stage 3 ....................................................................................................................................18 Stages