P11MCA1 & P8MCA1 - ADVANCED COMPUTER ARCHITECTURE UNIT V PROCESSORS AND MEMORY HIERARCHY ADVANCED PROCESSOR TECHNOLOGY: 1. Name the major processor families. Major processor families are CISC, RISC, Superscalar, VLIW, Super-pipelined, Vector and Symbolic processors. 2. What are the uses of scalar and vector processors? Scalar and Vector processors are used for numerical computation. 3. What are the uses of symbolic processors? Symbolic processors are used for Artificial Intelligence Applications. 4. What is the recent trend in processor technology? Clock rates of various processors are gradually increasing because of improvement in implementation technology. CPI rates are slowly decreased due to improvement in software and hardware technologies. 5. Compare the performance and features of various processor families based on their clock rates and processor rates. S.No Processor Family Features Clock rate CPI rate (MHz) 1. Complex Instruction Set Large, complex instruction set 33 - 50 1 – 20 Computers 2. Reduced Instruction Set Uses hardwired control, Small no. of 20 - 120 1 - 2 Computers instructions, Simple instructions 3. Superscalar Processors Multiple instruction issued at the 20 - 120 < 1, 2 same time 4. Very Long Instruction More functional units than super- Slow rates as High (more Word Processors scalars instructions access cycles 256-1024 bits per instruction should be for some Uses ROM and micro-programmed brought from instructions) control. ROM 5. Super-pipelined Use multi-phase clocks 100 - 500 High processors If multi-instruction issue is practiced CPI rate is low 6. Vector Super Computers Super-pipelined Low Use multiple functional units for scalar and vector operations Very costly (Refer figure above) 6. Write a note on Instruction pipelines. The execution cycle of a typical instruction consists of four phases: fetch, decode, execute and write-back. These instruction phases are executed by an instruction pipeline. The pipeline receives successive instructions from its input end and executes them in a streamlined, overlapped fashion as they flow through. A pipeline cycle is defined as the time required for each phase to complete its operation (per instruction), assuming equal delay in all phases. For full utilization of instruction pipeline, instruction issue rate should be 1. Otherwise the pipeline is under-utilized. Another reason for pipeline under-utilization could be combining pipeline stages. Eg. Fetch and decode, execute and write-back. In these cases the clock rate of the pipeline is halved. 7. Define Instruction Pipeline cycle. Instruction Pipeline cycle is the clock period of the instruction pipeline. 8. Define Instruction Issue Latency. Instruction Issue Latency is the time (in cylces) required between the issuing of two adjacent instructions. 9. Define Instruction Issue rate. Instruction Issue rate is the number of instructions issued per cycle. It is also called the degree of a superscalar processor. 10. Define Simple Operation Latency. Simple Operation Latency is the time taken to execute simple instructions (eg. Integer add, load, store etc) in cycles. 11. Define Complex Operation Latency. Complex Operation Latency is the time taken to execute complex instructions (eg. Divide, Cache misses, etc) in cycles. 12. Define Resource Conflict. Resource Conflict is the situation where two or more instructions demand use of the same functional unit at the same time. 13. What is a base scalar processor? A base scalar processor is a machine with one instruction issued per cycle, a one-cycle latency for a simple operation and a one-cycle latency between instruction issues.] 14. Write short notes on processors and co-processors. The CPU is a scalar processor. It may contain multiple functional units like integer ALU, floating point accelerator etc. Otherwise the special functional unit could be built on a co-processor and attached to the CPU. The co-processor executes instructions dispatched by the CPU, but it does not handle I/O operations. Eg. Floating point accelerator executing scalar data, vector processor executing vector operands, digital signal processor, Lisp processor for A.I applications. Co-processors are used to speed up numerical computations. They cannot be used alone. They act as a back-end to the central CPU and must be compatible with it. They are also called as attached processors or slave processors. Some of them may be more powerful than their hosts. Eg. Cray-Y-MP is attached to a mini computer. 15. Give some examples of co-processors for some processors and evaluate their performance metrics. Main processor name Co-processor name Speed (MHz) CPI for add CPI for log 1. Intel 8086/8088 Intel 8087 5 70 700 2. Intel 80286 Intel 80287 12.5 30 264 3. Intel 386DX Intel 387DX 33 12 210 4. Intel i486 Intel i486 33 8 171 5. MC68020/68030 MC68882 40 56 574 6. Intel 386DX Weitek 3167 33 6 365 INSTRUCTION SET ARCHITECTURE: 16. Comment on Instruction Set Architecture. The instruction set of a computer specifies the set of instructions provided to the user for programming the machine. The complexity of the instruction set is decided by its format, data format, addressing modes, general purpose registers, op-code specifications and flow control mechanisms. There are two schools of thought on the design of the instruction-set architectures of a computer system. They are : Complex Instruction set computers (CISC) Reduced Instruction set computers (RISC) 17. Write short notes on Evolution of CISC. In early days of computing, due to the high cost of hardware, instruction sets were simple. But now hardware cost has dropped. Moreover, complex High Level Languages have evolved, widening the gap between the semantics of the HLL and the machine. In order to implement such complex functions of the HLL, more and more functions have been added to be built into the hardware. So instruction sets have become very large and complex. Evolution of Microprogramming and its widespread use has also added to this situation. Implementation of user-defined instructions through micro-code has even been made possible. Such trends resulted in the evolution of CISC processors. 18. Mention the characteristics of CISC Instruction set. i) CISC instruction sets may contain 120 to 350 instructions ii) They follow a variable instruction / data format iii) Most systems are built with 8 to 24 general purpose registers iv) More than a dozen addressing modes are available v) Large number of memory reference operations are provided vi) They may implement HLL statements in hardware or firmware. vii) They allow vector and symbol processing. 19. Write short notes on Evolution of RISC. After two decades of computing with CISC processors, it was realized that only 25% of the instructions of a CISC instruction set were used about 95% of the time, while others were rarely used. Rarely used instructions demanded long micro-codes to execute and were elaborate. They also used valuable chip area. Hence it was decided to remove such instructions from the instruction set and implement them through software. As these were rarely used, it did not matter much even if the software implementations were slow. Moreover the available chip space could be used for building more powerful RISC / Superscalar processors with on-chip caches and floating point units. 20. Mention the characteristics of RISC Instruction set. i) RISC instruction sets contain less than 100 instructions. ii) They follow a fixed instruction format (32 bits) iii) Only 3 to 5 different addressing modes are available. iv) Most of the instructions are register based v) Memory is accessed by LOAD and STORE instructions only. vi) They follow hard-wired instruction control vii) The time taken to execute most instructions is 1 cycle. viii) Large number of registers are used for fast context-switching ix) The entire processor is etched on a single VLSI chip. 21. What are the advantages of RISC over CISC ? i) Higher clock rate and lower CPI ii) Higher MIPS rates iii) Separate instruction and data caches with different access paths improve performance. 22. Give some examples for CISC computers. Intel i486, M68040, VAX/8600, IBM 390 23. Give some examples for RISC computers. Intel i860, SPARC, MIPS R3000, IBM RS/6000 24. Give a few examples for RISC Scalar microprocessor families. Intel Processors: [Intel 4004(4-bit)], [8086, 8088, 80186, 80286(16-bit),], [80386, 80386, 80586 (32-bit)] Motorola Processors: MC6800 (8-bit), MC68000 (16-bit), MC68020, MC68030, MC68040 (32-bit) 25. Expand : SPARC Scalable Processor Architecture 26. What are remarkable features of RISC Scalar processors? Less frequently used operations are handled by software. They rely on good compilers. They use instruction level parallelism through pipelining. 27. What are the general features of RISC processors? Most RISC processors have 32-bit instructions. Their instruction sets consist of 50 to 125 instructions. Special floating point units are provided either offline or online. They have a large instruction cache, data cache and a memory management unit and support pipelining. 28. Tabulate the comparative features of RISC and CISC processor architectures Architectural Characteristic CISC RISC Instruction set size Large (120 – 350) Small ( < 100 ) Instruction format Variable (16 – 64 bits per Fixed (32 bits) register based instruction) instructions Addressing modes 12 – 24 3 – 5 General Purpose registers 8 – 24 32 – 192 Cache design Unified cache for data and Separate cache for data and instructions instructions. Clock rate 33-50 MHz 50-150 MHz Cycles per Instruction (CPI) 2 – 15 < 1.5 CPU control Micro-coded using control Hardwired, no control memory memory 29. Discuss the features of DEC VAX 8600 CISC processor architecture. The DEC VAX 8600 was introduced by Digital Equipment Corporation in the year 1985. It uses CISC architecture with micro-programmed control. The instruction set consists of 300 instructions with 20 different addressing modes. It interfaces with SBI and Unibus. The CPU consists of two functional units for concurrent execution of integer and floating point instructions.