3. PARALLEL STATEMENTS lvalue [<]= [#(number | (expr))] expr; lvalue [<]= [@ (event [{or event}])] expr; assign [(strength1, strength0)] WIRID = expr; wait (expr) sequential_statement initial sequential_statement -> EVENTID; always sequential_statement fork[: BLKID MODID [#({expr,})] INSTID [{declaration}]] Verilog HDL QUICK ([{expr,} | {.PORTID(expr),}]); [{sequential_statement}] REFERENCE CARD GATEID [(strength1, strength0)] [#delay] join [INSTID] ({expr,}); TASKID[({expr,})]; REVISION 1.1 defparam {HIERID = constexpr,}; disable BLKID | TASKID; strength ::= supply | strong | pull | weak | highz assign lvalue = expr; delay ::= number | PARID | ( expr [, expr [, expr]] ) () Grouping [ ] Optional deassign lvalue; {} Repeated | Alternative lvalue ::= bold As is CAPS User Identifier 4. GATE PRIMITIVES ID[range] | ID[expr] | {{lvalue,}} and (out, in1, ..., inN); nand (out, in1, ..., inN); event ::= [posedge | negedge] expr 1. MODULE or (out, in1, ..., inN); nor (out, in1, ..., inN); xor (out, in , ..., in ); xnor (out, in , ..., in ); module MODID[({PORTID,})]; 1 N 1 N 6. SPECIFY BLOCK STATEMENTS [input | output | inout [range] {PORTID,};] buf (out1, ..., outN, in); not (out1, ..., outN, in); specparam {ID = constexpr,}; [{declaration}] bufif0 (out, in, ctl); bufif1 (out, in, ctl); [{parallel_statement}] notif0 (out, in, ctl); notif1 (out, in, ctl); (terminal => terminal) = path_delay; [specify pullup (out); pulldown (out); ((terminal,} *> {terminal,}) = path_delay; {specify_statement} endspecify] [r]pmos (out, in, ctl); if (expr) (terminal [+|-]=> terminal) = path_delay; endmodule [r]nmos (out, in, ctl); if (expr) ({terminal,} [+|-]*> {terminal,}) = [r]cmos (out, in, nctl, pctl); range ::= [constexpr : constexpr] path_delay; [r]tran (inout, inout); [if (expr)] ([posedge|negedge] terminal => [r]tranif1 (inout, inout, ctl); (terminal [+|-]: expr)) = path_delay; 2. DECLARATIONS [r]tranif0 (inout, inout, ctl); [if (expr)] ([posedge|negedge] terminal *> parameter {PARID = constexpr,}; ({terminal,} [+|-]: expr)) = path_delay; wire | wand | wor [range] {WIRID,}; 5. SEQUENTIAL STATEMENTS $setup(tevent, tevent, expr [, ID]); reg [range] {REGID [range],}; ; $hold(tevent, tevent, expr [, ID]); integer {INTID [range],}; begin[: BLKID $setuphold(tevent, tevent, expr, expr [, ID]); time {TIMID [range],}; [{declaration}]] $period(tevent, expr [, ID]); [{sequential_statement}] real {REALID,}; $width(tevent, expr, constexpr [, ID]); end realtime {REALTIMID,}; $skew(tevent, tevent, expr [, ID]); if (expr) sequential_statement event {EVTID,}; [else sequential_statement] $recovery(tevent, tevent, expr [, ID]); task TASKID; case | casex | casez (expr) tevent ::= [posedge | negedge] terminal [{input | output | inout [range] {ARGID,};}] [{{expr,}: sequential_statement}] [&&& scalar_expr] [{declaration}] [default: sequential_statement] path_delay ::= begin endcase expr | (expr, expr [, expr [, expr, expr, expr]]) [{sequential_statement}] forever sequential_statement end terminal ::= ID[range] | ID[expr] endtask repeat (expr) sequential_statement function [range] FCTID; while (expr) sequential_statement {input [range] {ARGID,};} for (lvalue = expr; expr; lvalue = expr) [{declaration}] sequential_statement begin #(number | (expr)) sequential_statement [{sequential_statement}] © 1995 Qualis Design Corporation. Permission to end @ (event [{or event}]) sequential_statement reproduce and distribute strictly verbatim copies of this endfunction document in whole is hereby granted. See reverse side for additional information. © 1995 Qualis Design Corporation © 1995 Qualis Design Corporation 7. EXPRESSIONS $readmemh(“fname”, ID [, startadd [, stopadd]]); *$reset(1) Reset and run again *$sreadmemb(ID, startadd, stopadd {, string}); *$reset(0|1, expr) Reset with reset_value primary *$sreadmemh(ID, startadd, stopadd {, string}); *$reset_value Reset_value of last $reset unop primary *$reset_count # of times $reset was used 8.2. OUTPUT expr binop expr 8.5. MISCELLANEOUS $display[defbase]([fmtstr,] {expr,}); expr ? expr : expr $write[defbase] ([fmtstr,] {expr,}); $random[(ID)] primary ::= $strobe[defbase] ([fmtstr,] {expr,}); *$getpattern(mem) Assign mem content literal | lvalue | FCTID({expr,}) | ( expr ) $monitor[defbase] ([fmtstr,] {expr,}); $rtoi(expr) Convert real to integer $fdisplay[defbase] (fileno, [fmtstr,] {expr,}); $itor(expr) Convert integer to real 7.1. UNARY OPERATORS $fwrite[defbase] (fileno, [fmtstr,] {expr,}); $realtobits(expr) Convert real to 64-bit vector +, - Positive, Negative $fstrobe(fileno, [fmtstr,] {expr,}); $bitstoreal(expr) Convert 64-bit vector to real ! Logical negation $fmonitor(fileno, [fmtstr,] {expr,}); 8.6. ESCAPE SEQUENCES IN FORMAT STRINGS ~ Bitwise negation fileno = $fopen(“filename”); &, ~& Bitwise and, nand $fclose(fileno); \n, \t, \\, \” newline, TAB, ‘\’, ‘“‘ |, ~| Bitwise or, nor defbase ::= h | b | o \xxx character as octal value ^, ~^, ^~ Bitwise xor, xnor %% character ‘%’ 8.3. TIME %[w.d]e, %[w.d]E display real in scientific form 7.2. BINARY OPERATORS $time “now” as TIME %[w.d]f, %[w.d]F display real in decimal form Increasing precedence: $stime “now” as INTEGER %[w.d]g, %[w.d]G display real in shortest form %[0]h, %[0]H display in hexadecimal ?: if/else $realtime “now” as REAL $scale(hierid) Scale “foreign” time value %[0]d, %[0]D display in decimal || Logical or %[0]o, %[0]O display in octal && Logical and $printtimescale[(path)] Display time unit & precision %[0]b, %[0]B display in binary | Bitwise or %[0]c, %[0]C display as ASCII character ^, ^~ Bitwise xor, xnor $timeformat(unit#, prec#, “unit”, minwidth) Set time %t display format %[0]v, %[0]V display net signal strength & Bitwise and %[0]s, %[0]S display as string ==, != , ===, !== Equality 8.4. SIMULATION CONTROL %[0]t, %[0]T display in current time format <, <=, >, >= Inequality %[0]m, %[0]M display hierarchical name <<, >> Logical shift $stop Interrupt +, - Addition, Substraction $finish Terminate *, /, % Multiply, Divide, Modulo *$save(“fn”) Save current simulation 9. LEXICAL ELEMENTS *$incsave(“fn”) Delta-save since last save hierarchical identifier ::= {INSTID .} identifier 7.3. SIZES OF EXPRESSIONS *$restart(“fn”) Restart with saved simulation identifier ::= letter | _ { alphanumeric | $ | _} unsized constant 32 *$input(“fn”) Read commands from file sized constant as specified *$log[(“fn”)] Enable output logging to file escaped identifer ::= \ {nonwhite} *$nolog Disable output logging decimal literal ::= *$key[(“fn”)] Enable input logging to file [+|-]integer [. integer] [E|e[+|-] integer] i op j +,-,*,/,%,&,|,^,^~ max(L(i), L(j)) *$nokey Disable input logging op i +, -, ~ L(i) *$scope(hiername) Set scope to hierarchy based literal ::= i op j ===, !===, ==, != *$showscopes Scopes at current scope integer ‘ base {hexdigit | x | z} &&, ||, >, >=, <, <= 1 *$showscopes(1) All scopes at & below scope base ::= b | o | d | h op i &, ~&, |, ~|, ^, ~^ 1 *$showvars Info on all variables in scope comment ::= // comment newline i op j >>, << L(i) *$showvars(ID) Info on specified variable i ? j : k max(L(j), L(k)) *$countdrivers(net)>1 driver predicate comment block ::= /* comment */ {i,...,j} L(i) + ... + L(j) *$list[(ID)] List source of [named] block {i{j,...k}} i * (L(j)+...+L(k)) $monitoron Enable $monitor task i = j L(i) $monitoroff Disable $monitor task $dumpon Enable val change dumping © 1995 Qualis Design Corporation. Permission to $dumpoff Disable val change dumping 8. SYSTEM TASKS reproduce and distribute strictly verbatim copies of this $dumpfile(“fn”) Name of dump file document in whole is hereby granted. * indicates tasks not part of the IEEE standard $dumplimit(size) Max size of dump file but mentionned in the informative appendix. $dumpflush Flush dump file buffer Qualis Design Corporation $dumpvars(levels [{, MODID | VARID}]) Beaverton, OR USA 8.1. INPUT Variables to dump Phone: +1-503-531-0377 FAX: +1-503-629-5525 $readmemb(“fname”, ID [, startadd [, stopadd]]); $dumpall Force a dump now E-mail: [email protected] *$reset[(0)] Reset simulation to time 0 Also available: VHDL Quick Reference Card 1164 Packages Quick Reference Card © 1995 Qualis Design Corporation © 1995 Qualis Design Corporation.