GM IT I CM WAY - M AYO JN STirU TE ft? 16CHN 01.0 G Y I (Kil'IiOlD Al ; HlA j 0 The Research & Development of an Advanced Verification Infrastructure for ASIC Devices using SystemVerilog & the Verification Methodology Manual (VMM) In One Volume Michael Anthony McMahon B.Eng May 2010 Submitted for the Degree of Master of Engineering Submitted to: Galway Mayo Institute of Technology, Galway, Ireland Research carried out at: Chipright LTD, Galway, Ireland Declaration I hereby declare that the work presented in this thesis is my own and that it has not been previously used to obtain a degree in this institution or elsewhere. Michael Anthony McMahon ii Statement of Confidentiality The material contained in this thesis should not be used, sold, assigned, or disclosed to other person(s), organisation(s) or corporation(s) without the written conscnt of both Chipright Ltd, and Niall O’Keeffe. Galway Mayo Institute of Technology: Contact: Niall O’Keeffe Tel: +35391 742057 Email: niall.okeeffe(c/).amit.ie Chipright: Contact Kevin Keane Tel:+91 444168 Email kcvin.koancfrfjclnpritzlU.com Prologue The research described in this thesis has been conducted over a 24-month period as part of a college/industry partnership project. This project was funded under the Innovation Partnership research grants scheme administered by Enterprise Ireland. The aim of the project is to research and develop an Advanced Verification Infrastructure using SystemVerilog and the Verification Methodology Manual ( VMM). Acknowledgements I would like to thank the following people for their support and encouragement during the course of this project. I would like to thank: First and foremost, my supervisor, Niall O’Keeffe of the Department of Electronic Engineering in GMIT, for his supervision, guidance, inspiration, and his constructive suggestions throughout this research study. Without his support and encouragement this research would not have been done. Emer O’Mahony for all her help and support throughout the course of my studies. The senior engineers from Chipright Ltd. for their help and support while doing this project. They were of great help in teaching me to become familiar with SystemVerilog, helping with developing the testbench and giving useful insights into the practical and potential implementations of SystemVerilog. I would also like to give a special mention to my parents, who have helped and guided me through my time at college in GMIT. Abstract In digital design much of the focus and attention in the past has been towards developing languages and tools primarily for use in designing an ASIC device. Today, the single biggest problem in digital design is the time that is spent in the Verification process. With this in mind the key EDA companies have focused a large proportion of their research and development budgets towards supporting new verification languages and methodologies, namely, SystemVerilog and OpenVera. SystemVerilog is the industry's first unified hardware description and verification language (HDVL). Along with developing SystemVerilog, the EDA companies have developed methodologies to support the language. The two main methodologies are the Synopsys’s Verification Methodology Manual and Cadence/Mentor Open Verification Methodology. These methodologies are geared towards the implementation of functional coverage-points; use of assertion based coverage and constrained random test techniques. This thesis outlines a VMM style test bench architecture that is structured to gain maximum efficiency from both constrained random and directed test case development. This thesis describes how directed and constrained random tests can be implemented inside a reusable directory structure that takes full advantage of the coverage and assertion techniques. This thesis uses an IEEE-754 compliant floating-point adder model as part of a case study that illustrates a complete set of results extrapolated from using this test bench structure. An Integrated Inter Circuit (I2C) verification component has also been implemented and used to test the reusability of the test bench structure. This thesis reviews the use of formal verification within the digital design community. Formal methods such as model checking, equivalence checking and deductive reasoning have become increasingly popular verification techniques. These methods are investigated to see if they could be used as alternative verification techniques within the verification environment. TABLE OF CONTENTS LIST OF FIGURES..........................................................................................................X LIST OF TABLES........................................................................................................ XV CHAPTER 1 INTRODUCTION.....................................................................................1 1.1 Thesis Motivation................................................................................................ 1 1.2 Thesis Contributions...........................................................................................2 1.3 Thesis Structure................................................................................................... 3 CHAPTER 2 REVIEW OF ASIC VERIFICATION TECHNIQUES.....................6 2.1 Introduction..........................................................................................................6 2.2 The Goal of Verification.....................................................................................8 2.3 The ASIC Verification Challenge...................................................................11 2.4 Functional Verification.....................................................................................13 2.5 The Bottleneck in ASIC Verification..............................................................15 2.6 Conclusion...........................................................................................................17 CHAPTER 3 CURRENT VERIFICATION LANGUAGES, METHODOLOGIES AND TRENDS.................................................................................................................. 19 3.1 Introduction........................................................................................................19 3.2 SystemVerilog.....................................................................................................19 3.3 Verilog................................................................................................................. 20 3.4 OpenVera............................................................................................................21 3.5 History of Verilog and SystemVerilog............................................................21 3.6 SystemVerilog Extensions to Verilog 2001.................................................... 23 3.7 Methodologies and Tools..................................................................................30 3.8 SystemVerilog Growth within the Verification Industry...........................37 3.9 Conclusion...........................................................................................................39 CHAPTER 4 VMM BASED VERIFICATION ENVIRONMENT.......................40 4.1 Introduction........................................................................................................40 4.2 Device Under Test (Floating-point Adder Model)....................................... 42 4.3 Designing a Verification Environment...........................................................44 4.4 Floating-point Adder Interface....................................................................... 45 4.5 Data Class............................................................................................................49 4.6 Bus Functional Model (BFM).......................................................................... 54 vii 4.7 The Environment............................................................................................. 57 4.8 Program and Top File.....................................................................................62 4.9 Testing of Floating-point Adder Model....................................................... 64 4.10 Conclusions.......................................................................................................70 CHAPTER 5 ADVANCED VERIFICATION ENVIRONEMENT....................... 72 5.1 Introduction......................................................................................................72 5.2 Directory Structure......................................................................................... 73 5.3 Test Bench Architecture.................................................................................76 5.4 Reference Model...............................................................................................77 5.5 Scoreboard........................................................................................................ 80 5.6 Test Case Library............................................................................................ 82 5.7 Functional Coverage....................................................................................... 91 5.8 VMM Planner...................................................................................................95 5.9 Testing the Floating-point Adder................................................................ 100 5.10 Conclusion......................................................................................................