COP8780C/COP8781C/COP8782C 8-Bit One-Time Programmable (OTP) Microcontroller August 1996 COP8780C/COP8781C/COP8782C 8-Bit One-Time Programmable (OTP) Microcontroller General Description Y Schmitt trigger inputs on Port G Y MICROWIRE/PLUS serial I/O The COP8780C, COP8781C and COP8782C are members Y Packages: of the COPSTM 8-bit microcontroller family. They are fully Ð 44 PLCC, OTP, Emulates COP880C, 36 I/O pins static microcontrollers, fabricated using double-metal, dou- Ð 40 DIP, OTP, Emulates COP880C, 36 I/O pins ble poly silicon gate microCMOS EPROM technology. Ð 28 DIP, OTP, Emulates COP820C/840C/881C, These devices are available as UV erasable or One Time 24 I/O pins Programmable (OTP). These low cost microcontrollers are Ð 20 DIP, OTP, Emulates COP822C/842C, 16 I/O pins complete microcomputers containing all system timing, in- Ð 28 SO, 20 SO, OTP terrupt logic, EPROM, RAM, and I/O necessary to imple- Ð 44 LDCC, UV Erasable ment dedicated control functions in a variety of applications. Ð 40 CERDIP, 28 CERDIP, 20 CERDIP, UV Erasable Features include an 8-bit memory mapped architecture, MI- CROWIRE/PLUSTM serial I/O, a 16-bit timer/counter with associated 16-bit autoreload/capture register, and a multi- CPU/Instruction Set Features sourced interrupt. Each I/O pin has software selectable op- Y 1 ms instruction cycle time tions to adapt the device to the specific application. These Y Three multi-source interrupts servicing devices operate over a voltage range of 4.5V to 6.0V. An Ð External interrupt with selectable edge efficient, regular instruction set operating at a 1 ms instruc- Ð Timer interrupt tion cycle rate provides optimal throughput. Ð Software interrupt The COP8780C, COP8781C and COP8782C can be config- Y Versatile and easy to use instruction set ured to EMULATE the COP880C, COP840C and COP820C Y 8-bit Stack Pointer (SP)Ðstack in RAM microcontrollers. Y Two 8-bit Register Indirect Data Memory Pointers (B and X) Key Features Y 16-bit multi-function timer supporting Fully Static CMOS Ð PWM mode Y Low current drain (typically k 1 mA) Ð External event counter mode Y Extra-low current static HALT mode Ð Input capture mode Y Single supply operation: 4.5V to 6.0V Y Crystal, RC or External Oscillator, user configurable Y Temperature range: b40§Ctoa85§C Y 4 kbytes on-chip OTP EPROM with security feature Y 128 or 64 bytes of on-chip RAM, user configurable Development Support Y Emulation device for the COP880C, COP840C, and I/O Features COP820C Y Memory-mapped I/O Y Real-time emulation and full program debug offered by Y Software selectable I/O options (TRI-STATEÉ, Push- MetaLink development system Pull, Weak Pull-Up Input, High Impedance input) Block Diagram TL/DD/11299±1 FIGURE 1. Block Diagram TRI-STATEÉ is a registered trademark of National Semiconductor Corporation. COPSTM microcontrollers, MICROWIRETM, MICROWIRE/PLUSTM and WATCHDOGTM are trademarks of National Semiconductor Corporation. iceMASTERTM is a trademark of MetaLink Corporation. C1996 National Semiconductor Corporation TL/DD11299 RRD-B30M96/Printed in U. S. A. http://www.national.com Connection Diagrams TL/DD/11299±4 Top View Order Number COP8780C-XXX/V or COP8780C-XXX/EL TL/DD/11299±3 See NS Package Number EL40C or V44A Top View Order Number COP8780C-XXX/N or COP8780C-XXX/J See NS Package Number J40AQ or N40A TL/DD/11299±5 Top View Order Number COP78782C/XXX/J, COP8782C-XXX/N TL/DD/11299±6 or COP8782C-XXX/WM Top View See NS Package Number J20AQ, M20B or N20B Order Number COP8781C-XXX/J, COP8781C-XXX/N or COP8781C-XXX/WM See NS Package Number J28AQ, M28B or N28B FIGURE 3. Connection Diagrams http://www.national.com 2 COP8780C/COP8781C/COP8782C Absolute Maximum Ratings If Military/Aerospace specified devices are required, Total Current into VCC Pin (Source) 50 mA please contact the National Semiconductor Sales Total Current out of GND Pin (Sink) 60 mA Office/Distributors for availability and specifications. Storage Temperature Range b65§Ctoa150§C Supply Voltage (V )7V CC Note: Absolute maximum ratings indicate limits beyond Programming Voltage VPP (RESET pin) which damage to the device may occur. DC and AC electri- and ME (pin G6) 13.4V cal specifications are not ensured when operating the de- Voltage at any Pin b0.3V to VCC a 0.3V vice at absolute maximum ratings. DC Electrical Characteristics COP87XXC; b40§C s TA s a85§C unless otherwise specified Parameter Condition Min Typ Max Units Operating Voltage 4.5 6.0 V Power Supply Ripple (Note 1) Peak to Peak 0.1 VCC V Supply Current CKI e 10 MHz (Note 2) VCC e 6V, tc e 1 ms21mA HALT Current (Note 3) VCC e 6V, CKI e 0 MHz 10 mA Input Levels RESET, CKI Logic High 0.9 VCC V Logic Low 0.1 VCC V All Other Inputs Logic High 0.7 VCC V Logic Low 0.2 VCC V Hi-Z Input Leakage VCC e 6.0V b2 a2 mA Input Pullup Current VCC e 6.0V, VIN e 0V b40 b250 mA G Port Input Hysteresis (Note 6) 0.05 VCC V Output Current Levels D Outputs Source VCC e 4.5V, VOH e 3.8V b0.4 mA Sink VCC e 4.5V, VOL e 1.0V 10 mA All Others Source (Weak Pull-Up) VCC e 4.5V, VOH e 3.2V b10 b110 mA Source (Push-Pull Mode) VCC e 4.5V, VOH e 3.8V b0.4 mA Sink (Push-Pull Mode) VCC e 4.5V, VOL e 0.4V 1.6 mA TRI-STATE Leakage b2.0 a2.0 mA Allowable Sink/Source Current per Pin D Outputs (Sink) 15 mA All Others 3mA Maximum Input Current (Notes 4, 6) Room Temp 200 mA without Latchup (Room Temp) g RAM Retention Voltage, Vr 2.0 V (Note 5) Input Capacitance (Note 6) 7 pF Load Capacitance on D2 (Note 6) 1000 pF Note 1: Rate of voltage change must be less than 0.5V/ms. Note 2: Supply current is measured after running 2000 cycles with a square wave CKI input, CKO open, inputs at rails and outputs open. Note 3: The HALT mode will stop CKI from oscillating in the RC and the crystal configurations. Halt test conditions: All Inputs tied to VCC. L, C, and G port I/O's configured as outputs and programmed low; D outputs programmed low; the window for UV erasable packages is completely covered with an opaque cover to prevent light from falling onto the die during HALT mode test. Parameter refers to HALT mode entered via setting bit 7 of the G Port data register. Note 4: Pins G6 and RESET are designed with a high voltage input network for factory testing. These pins allow input voltages greater than VCC and the pins will have sink current to VCC when biased at voltages greater than VCC (the pins do not have source current when biased at a voltage below VCC). The effective resistance to VCC is 750X (typ). These two pins will not latch up. The voltage at the pins must be limited to less than 14V. Note 5: To maintain RAM integrity, the voltage must not be dropped or raised instantaneously. Note 6: Parameter characterized but not tested. 3 http://www.national.com COP8780C/COP8781C/COP8782C AC Electrical Characteristics b40§C k TA k a85§C unless otherwise specified Parameter Condition Min Typ Max Units Instruction Cycle Time (tc) Crystal/Resonator or External Clock VCC t 4.5V 1 DC ms R/C Oscillator Mode VCC t 4.5V 3 DC ms CKI Clock Duty Cycle (Note 7) fr e Max 45 55 % Rise Time (Note 7) fr e 10 MHz Ext Clock 12 ns Fall Time (Note 7) fr e 10 MHz Ext Clock 8 ns Inputs tSETUP VCC t 4.5V 200 ns tHOLD VCC t 4.5V 60 ns Output Propagation Delay CL e 100 pF, RL e 2.2 kX tPD1,tPD0 SO, SK VCC t 4.5V 0.7 ms All Others VCC t 4.5V 1 ms MICROWIRETM Setup Time (tUWS) 20 ns MICROWIRE Hold Time (tUWH) 56 ns MICROWIRE Output Propagation Delay (tUPD) 220 ns Input Pulse Width Interrupt Input High Time 1 tc Interrupt Input Low Time 1 tc Timer Input High Time 1 tc Timer Input Low Time 1 tc Reset Pulse Width 1.0 ms Note 7: Parameter guaranteed by design, but not tested. tc e Instruction Cycle Time. Timing Diagram TL/DD/10802±2 FIGURE 2. MICROWIRE/PLUS Timing http://www.national.com 4 Pin Descriptions VCC and GND are the power supply pins. Pins G1 and G2 currently do not have any alternate func- CKI is the clock input. This can come from an external tions. source, a R/C generated oscillator or a crystal (in conjunc- PORT D is an 8-bit output port that is preset high when tion with CKO). See Oscillator description. RESET goes low. Care must be exercised with the D2 pin RESET is the master reset input. See Reset description. operation. At reset, the external load on this pin must en- sure that the output voltage stay above 0.7 V to prevent PORT I is an 8-bit Hi-Z input port. The 28-pin device does CC the chip from entering special modes. Also, keep the exter- not have a full complement of PORT I pins. The unavailable nal loading on D2 to less than 1000 pF. pins are not terminated i.e., they are floating.