MODELLING AND APPLICATIONS OF MOS VARACTORS FOR HIGH-SPEED CMOS CLOCK AND DATA RECOVERY by Pedram Sameni M.A.Sc., Simon Fraser University, 2002 B.Sc., University of Tehran, 1999 THESIS SUBMITTED IN PARTIAL FULFILMENT OF THE REQUIREMENTS FOR THE DEGREE OF Doctor of Philosophy in The Faculty of Graduate Studies (Electrical and Computer Engineering) The University of British Columbia (Vancouver) February 2008 © Pedram Sameni, 2008 Abstract The high-speed clock and data recovery (CDR) circuit is a key building block of modern communication systems with applications spanning a wide range from wireline long-haul networks to chip-to-chip and backplane communications. In this dissertation, our focus is on the modelling, design and analysis of devices and circuits used in this versatile system in CMOS technology. Of these blocks, we have identified the voltage-controlled oscillator (VCO) as an important circuit that contributes to the total noise performance of the CDR. Among different solutions known for this circuit, LC-VCO is acknowledged to have the best phase noise performance, due to the filtering characteristic of the LC tank circuit. We provide details on modelling and characterization of a special type of varactor, the accumulation-mode MOS varactor, used in the tank circuit as a tuning component of these types of VCOs. We propose a new sub-circuit model for this type of varactor, which can be easily migrated to other technologies as long as an accurate model exists for MOS transistors. The model is suitable whenever the numerical models have convergence problems and/or are not defined for the specific designs (e.g., minimum length structures). The model is verified directly using measurement in a standard CMOS 0.13µm process, and indirectly by comparing the tuning curves of an LC-VCO designed in CMOS 0.13µm and 0.18µm processes. Using a varactor, a circuit technique is proposed for designing a narrowband tuneable clock buffer, which can be used in a variety of applications including the CDR system. The buffer automatically adjusts its driving bandwidth to that of the VCO, using the same control voltage that controls the frequency of the VCO. In addition, a detailed analysis of the impact of large output signals on the tuning characteristics of the LC-VCO is performed. It is shown that the oscillation frequency of the VCO deviates from that of an LC tank. ii Table of Contents Abstract............................................................................................................... ii Table of Contents .............................................................................................. iii List of Tables ...................................................................................................... v List of Figures.................................................................................................... vi List of Abbreviations and Terms....................................................................... x Acknowledgements.......................................................................................... xii Chapter 1 Introduction ....................................................................................... 1 1.1 Clock and Data Recovery Methods.................................................... 3 1.2 Why CMOS? ...................................................................................... 5 1.3 Contributions ...................................................................................... 7 1.3.1 A New Varactor Model .................................................................... 8 1.3.2 High-speed Tuneable Driver/Buffer................................................. 8 1.3.3 Effect of Large Signals in LC-VCO Tuning Characteristics ............. 8 1.4 Organization of Thesis ....................................................................... 9 Chapter 2 Background and Comparison of VCOs and Phase Detectors........................................................................................................... 10 2.1 VCO Phase Noise and its Impact on System Operation .................. 11 2.1.1 Comparison of Popular VCO Architectures................................... 15 2.1.2 LC-Based VCOs ........................................................................... 18 2.2 CDR Phase Detectors ...................................................................... 21 2.3 Linear and Bang-Bang CDR Models ................................................ 27 2.3.1 Linear CDR Model ........................................................................ 28 2.3.2 Bang-Bang PD Model ................................................................... 33 2.4 Time-Domain Comparison of the Two PDs ...................................... 36 2.4.1 Time-Domain Simulations of Bang-Bang and Linear CDRs with Noise Considerations ............................................................ 37 2.5 Summary and Conclusion ................................................................ 39 Chapter 3 Modelling and Characterization of MOS Varactors...................... 41 3.1 Varactors.......................................................................................... 42 3.2 VCO Tuning Characteristics............................................................. 45 3.3 Characterization of AMOS Varactors ............................................... 49 3.3.1 De-embedding Technique............................................................. 50 3.3.2 Parameter Extraction Procedure................................................... 53 3.4 Varactor Modelling ........................................................................... 55 iii 3.5 Experimental and Simulation Results............................................... 58 3.5.1 Experimental Results in a Standard 0.13µm CMOS Process ....... 58 3.5.2 Simulation Results in a Standard 0.18µm CMOS Process ........... 62 3.6 Conclusion ....................................................................................... 64 Chapter 4 High-Speed Tuneable Narrowband CMOS Driver......................... 67 4.1 Background ...................................................................................... 69 4.2 Proposed Solution............................................................................ 73 4.2.1 Design Example............................................................................ 75 4.3 Simulation Results............................................................................ 77 4.4 Conclusion ....................................................................................... 81 Chapter 5 Impact of Large Signals on LC-VCO with Accumulation MOS Varactors.................................................................................................. 83 5.1 MOS Varactors................................................................................. 85 5.2 MOS Varactors in LC-VCOs............................................................. 87 5.2.1 Small-signal Analysis .................................................................... 89 5.2.2 Large-signal Analysis.................................................................... 90 5.3 Simulation Results............................................................................ 94 5.4 Conclusion ..................................................................................... 100 Chapter 6 Conclusions .................................................................................. 102 6.1 Accomplishments ........................................................................... 103 References ...................................................................................................... 107 Appendices ..................................................................................................... 116 Appendix A – Jitter Terminology.................................................................... 116 Appendix B – Flicker Noise Generation and Modelling for CDR Applications.................................................................................... 118 Appendix C – The Analog Verilog Code for the AMOS Varactor................... 123 iv List of Tables Table 2-1. Comparison between phase noises of different wireless standards............................................................................................. 13 Table 2-2. Comparison of existing popular oscillator architectures..................... 18 Table 4-1. Summary of bandwidth extension using the series-peaking technique............................................................................................. 72 Table 4-2. Resonance frequency and gain at five voltages on the control line for typical and two extreme corners .............................................. 80 v List of Figures Figure 1-1. CDR is used whenever the data is sent serially without the timing information. (a) Original serialized data at the transmitter, (b) same data but distorted and mixed with noise at the receiver.......... 2 Figure 1-2. Filter-based clock and data recovery.................................................. 3 Figure 1-3. Generic closed-loop solution for clock and data recovery .................. 4 Figure 2-1. GSM channel around 1.8 GHz ......................................................... 12 Figure 2-2. Channel interference in the case of larger-than-expected phase noise ......................................................................................... 12 Figure 2-3. A block diagram of a frequency synthesizer....................................