Freescale Semiconductor, Inc... MOTOROLA ADDRESS GENERATIONUNIT(AGU) ADDRESS GENERATIONUNIT (AGU) 4-1 Freescale Semiconductor,Inc. F o r M o r G e o I SECTION 4 n t f o o : r w m w a t w i o . f n r e O e n s c T a h l i e s . c P o r o m d u c t , Freescale Semiconductor, Inc. SECTION CONTENTS 4.1 INTRODUCTION . 4-3 4.2 ADDRESS REGISTER FILE (Rn) . 4-3 4.3 OFFSET REGISTER FILE (Nn) . 4-3 4.4 MODIFIER REGISTER FILE (Mn) . 4-4 4.5 TEMPORARY ADDRESS REGISTER . 4-4 4.6 AGU STATUS REGISTER . 4-5 4.7 PC RELATIVE ADDRESSING UNIT . 4-6 4.8 SECONDARY OFFSET ADDER UNIT . 4-6 4.9 MODULO ARITHMETIC UNIT . 4-6 . 4.10 ADDRESSING MODES . 4-7 c 4.11 ADDRESS MODIFIER TYPES . 4-12 n I , r o t c u d n o c i m e S e l a c s e e r F 4 - 2 ADDRESS GENERATION UNIT (AGU) MOTOROLA For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. INTRODUCTION 4.1 INTRODUCTION The major components of the AGU are: • Address Register Files • Offset Register Files • Modifier Register Files • Address Arithmetic Unit Containing: – Temporary Address Register – Local Status Register – PC Relative Addressing Unit . – Secondary Offset Adder Unit . – Modulo Arithmetic Unit c – Address Output Multiplexer n I A block diagram of the AGU is shown in Figure 4-1. , r o 4.2 ADDRESS REGISTER FILE (Rn) t c The Address Register File consists of four, sixteen-bit registers. The file contains the ad- u dress registers R0-R3 which usually contain addresses used as pointers to memory. Each d register may be read or written by the Global Data Bus. High speed access to the XAB1 n o and XAB2 buses is required to allow maximum access time for the internal and external c i X Data Memory and Program Memory. Each address register may be used as an input to the modulo arithmetic unit for a register update calculation. Each register may be written m e by the Global Data Bus or by the output of the modulo arithmetic unit. S R2, R3 and Temp may be used as inputs to a separate offset adder for an independent e l register update calculation. This special update calculation occurs during parallel, dual a reads (using R3) and during offset by absolute immediate offsets (using R2+$xx). c s e CAUTION e Due to pipelining, if an address register (M, N, or R) is changed r F with a MOVE instruction, the new contents will not be available for use as a pointer until the second following instruction. 4.3 OFFSET REGISTER FILE (Nn) The Offset Register File consists of four, sixteen-bit registers. The file contains the offset registers N0-N3 and usually contains offset values used to update address pointers. Each offset register may be read or written by the Global Data Bus. Each offset register is read when the same number address register is read and used as an input to the modulo arith- metic unit. MOTOROLA ADDRESS GENERATION UNIT (AGU) 4 - 3 For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. MODIFIER REGISTER FILE (Mn) GDB(0:15) PDB(0:15) UB(0:15) temp Modifier Offset . Register Register . Address Register File File File c m0 r0 n n0 I ctrl ctrl ctrl ctrl m1 n1 Address r1 , r Arithmetic m2 n2 r2 o Unit t m3 n3 r3 c u n3 only d NB(0:15) n o RB(0:15) MB(0:15) c i m e S XAB2(0:15)XAB1(0:15) PAB(0:15) e l a Figure 4-1 AGU Block Diagram c s e e r 4.4 MODIFIER REGISTER FILE (Mn) F The Modifier Register File consists of four, 16-bit registers. The file contains the modifier registers M0-M3 and usually specifies the type of arithmetic used to modify an address register during address register update calculations. Each modifier register may be read or written by the Global Data Bus. Each modifier register is read when the same number address register is read and used as an input to the modulo arithmetic unit. Each modifier register is preset to $FFFF during a processor reset. 4.5 TEMPORARY ADDRESS REGISTER The temporary address register, Temp, is a 16-bit register which provides for: 4 - 4 ADDRESS GENERATION UNIT (AGU) MOTOROLA For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. AGU STATUS REGISTER 1. temporary storage for an absolute address loaded from the Program Data Bus, 2. the immediate data loaded from the Global Data Bus, 3. Address Register Indirect with Immediate Displacement addressing mode, 4. the contents of A1 or B1 registers used by the Accumulator Register Indirect Addressing mode, or 5. the output of the modulo arithmetic unit. The modulo arithmetic unit output is loaded into the Temp register during the pre-update . cycle of the indexed by offset addressing mode, of the pre-decrement addressing mode, . and during the LEA instruction. In each of these addressing modes, an address register c n is accessed, updated by the modulo arithmetic unit, and stored in Temp in one instruction I cycle. In the following cycle, the content of Temp is used to address the X memory. For , r all absolute addressing modes, the address of the operand is written into Temp and then o t used to address X: or P: memory. c u 4.6 AGU STATUS REGISTER d n The 3-bit local status register in the AGU, which cannot be accessed by the user, will be o updated after every register update; i.e., only those addressing modes that update the ad- c i dress register regardless of memory access type. m Updating of the local status register is as follows: e S ← sr_v set if the modulo circuit performed a wrap, clear otherwise. e l sr_z ← set if the result of the address update is zero, clear otherwise. a ← c sr_n set if the result of the address update is negative, clear otherwise. s The CHKAAU instruction will copy the AGU status register to SR as follows: e e ← r V sr_v F Z ← sr_z N ← sr_n During double parallel reads, only the update of the address register used for the first par- allel read (not r3) will affect the local status register. Note: Only the V, Z, N bits of SR will be changed. MOTOROLA ADDRESS GENERATION UNIT (AGU) 4 - 5 For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. PC RELATIVE ADDRESSING UNIT 4.7 PC RELATIVE ADDRESSING UNIT The PC Relative Addressing Unit performs the PC relative address computation with sign extension done on the program address offset. The result is gated onto the Program Ad- dress Bus by a control signal from the program controller. 4.8 SECONDARY OFFSET ADDER UNIT The Secondary Offset Adder Unit is used for an address update calculation during double data memory read instructions, or for the addition of address register and immediate dis- placement. 4.9 MODULO ARITHMETIC UNIT c The Modulo Arithmetic Unit contains one 16-bit full adder (called the offset adder) which n I may add one, subtract one, or add the contents of the respective signed offset register N , to the contents of the selected address register. A second full adder (called the modulo r o adder) adds the summed result of the first full adder to a modulo value M or minus M, t where M is stored in the respective modifier register. A third full adder (called the reverse c u carry adder) adds the constant one, minus one, the offset N (stored in the respective offset d register) to the selected address register with the carry propagating in the reverse direc- n tion, from the most significant bit to the least. The offset adder and the reverse carry adder o c are in parallel and share common inputs. Test logic determines which of the three i summed outputs of the full adders is output to the address register file or temporary reg- m ister. e S The modulo arithmetic unit can update one address register, Rn, during one instruction e cycle. It is capable of performing linear, reverse carry, and modulo arithmetic. The con- l a tents of the selected modifier register specifies the type of arithmetic required in an ad- c dress register update calculation. The modifier value is decoded in the modulo arithmetic s unit and affects the unit’s operation. The modulo arithmetic unit’s operation is data-depen- e e dent and requires execution cycle decoding of the selected modifier register contents. r Note that for dual reads, there is no modulo capability for an R3 update, linear arithmetic F will be used. The output of the offset adder gives the result of linear arithmetic (e.g. Rn+1; Rn+N) and is selected as the modulo arithmetic unit’s output for linear arithmetic addressing modifi- ers. The reverse carry adder performs the required operation for reverse carry arithmetic and its output is selected as the modulo arithmetic unit’s output for reverse carry address- ing modifiers. Reverse carry arithmetic is useful for 2k point FFT addressing. For modulo arithmetic, the modulo arithmetic unit will perform the function (Rn+N) modulo M where N can be one, minus one, or the contents of the offset register Nn.