ELEC 5200-001/6200-001 Computer Architecture and Design Fall 2013 Datapath and Control (Chapter 4) Vishwani D. Agrawal & Victor P. Nelson Department of Electrical and Computer Engineering Auburn University, Auburn, AL 36849 Fall 2013, . ELEC 5200-001/6200-001 Lecture 5 1 Von Neumann Kitchen ALU Start Control My choice Registers PC Processor Program Data Input Memory Output Fall 2013, . ELEC 5200-001/6200-001 Lecture 5 2 Where Does It All Begin? In a register called program counter (PC). PC contains the memory address of the next instruction to be executed. In the beginning, PC contains the address of the memory location where the program begins. Fall 2013, . ELEC 5200-001/6200-001 Lecture 5 3 Where is the Program? Processor Memory Program counter (register) Machine code of program Start address Fall 2013, . ELEC 5200-001/6200-001 Lecture 5 4 How Does It Run? Start PC has memory address where program begins Fetch instruction word from memory address in PC and increment PC ← PC + 4 to point to next instruction Decode instruction Execute instruction Save result in register or memory No Yes Program STOP complete? Fall 2013, . ELEC 5200-001/6200-001 Lecture 5 5 Datapath and Control Datapath: Memory, registers, adders, ALU, and communication buses. Each step (fetch, decode, execute, save result) requires communication (data transfer) paths between memory, registers and ALU. Control: Datapath for each step is set up by control signals that set up dataflow directions on communication buses and select ALU and memory functions. Control signals are generated by a control unit consisting of one or more finite- state machines. Fall 2013, . ELEC 5200-001/6200-001 Lecture 5 6 Datapath for Instruction Fetch Add 4 Instruction Instruction word to PC Address Memory control unit and registers Fall 2013, . ELEC 5200-001/6200-001 Lecture 5 7 Register File: A Datapath Component 5 reg 1 32 Read reg 1 data registers 5 reg 2 32 Registers (reg. file) Write 5 register 32 reg 2 data Write data 32 RegWrite from control Fall 2013, . ELEC 5200-001/6200-001 Lecture 5 8 Multi-Operation ALU Operation select Operation select ALU function from control 000 AND 001 OR 3 010 Add zero 110 Subtract ALU 111 Set on less than result overflow zero = 1, when all bits of result are 0 Fall 2013, . ELEC 5200-001/6200-001 Lecture 5 9 R-Type Instructions Also known as arithmetic-logical instructions add, sub, slt Example: add $t0, $s1, $s2 – Machine instruction word 000000 10001 10010 01000 00000 100000 opcode $s1 $s2 $t0 function – Read two registers – Write one register – Opcode and function code go to control unit that generates RegWrite and ALU operation code. Fall 2013, . ELEC 5200-001/6200-001 Lecture 5 10 Datapath for R-Type Instruction 000000 10001 10010 01000 00000 100000 Operation opcode $s1 $s2 $t0 function (add) select from control (add) 5 Read $s1 10001 32 3 register numbers 5 zero $s2 32 Registers ALU result 10010 (reg. file) 32 Write reg. 5 overflow $t0 number 01000 Write data 32 RegWrite from control activated Fall 2013, . ELEC 5200-001/6200-001 Lecture 5 11 Load and Store Instructions I-type instructions lw $t0, 1200 ($t1) # incr. in bytes 100011 01001 01000 0000 0100 1011 0000 opcode $t1 $t0 1200 sw $t0, 1200 ($t1) # incr. in bytes 101011 01001 01000 0000 0100 1011 0000 opcode $t1 $t0 1200 Fall 2013, . ELEC 5200-001/6200-001 Lecture 5 12 Datapath for lw Instruction 100011 01001 01000 0000 0100 1011 0000 opcode $t1 $t0 1200 MemWrite Operation select 5 from control Read $t1 01001 (add) register 32 3 Read numbers data 5 zero 32 Registers ALU result (reg. file) Addr. Data overflow memory Write reg. 5 $t0 number 01000 Write Write data data 32 32 RegWrite from control MemRead activated Sign activated extend 16 mem. data to $t0 0000 0100 1011 0000 0000 01001011 Fall 2013, . ELEC 5200-001/6200-001 Lecture 5 13 Datapath for sw Instruction 101011 01001 01000 0000 0100 1011 0000 MemWrite opcode $t1 $t0 1200 activated Operation 5 select Read $t1 from control 01001 register 32 3 (add) Read numbers zero data 5 $t0 32 Registers ALU result 01000 (reg. file) Addr. Data overflow Write reg. 5 memory number 32 Write Write data $t0 data to mem. data 32 32 RegWrite MemRead from control Sign extend 16 0000 0100 1011 0000 0000 01001011 Fall 2013, . ELEC 5200-001/6200-001 Lecture 5 14 Branch Instruction (I-Type) beq $s1, $s2, 25 # if $s1 = $s2, advance PC through 25 instructions 16-bits 000100 10001 10010 0000 0000 0001 1001 opcode $s1 $s2 25 Note: Can branch within ± 215 words from the current instruction address in PC. Fall 2013, . ELEC 5200-001/6200-001 Lecture 5 15 Datapath for beq Instruction 16-bits 000100 10001 10010 0000 0000 0001 1001 opcode $s1 $s2 25 Operation 5 select Read $s1 10001 from control (subtract) register numbers 32 3 5 $s2 32 Registers To branch 10010 zero (reg. file) control ALU 5 result logic Write reg. 32 number overflow Write data PC+4 Branch 32 RegWrite From instruction 32 target from control fetch datapath Add 16 Sign Shift 32 extend 32 left 2 32 0000 0000 0001 1001 0000 0000 Fall 2013, . ELEC 5200-001/6200-001 Lecture 5 16 J-Type Instruction j 2500 # jump to instruction 2,500 26-bits 000010 0000 0000 0000 0010 0111 0001 00 opcode 2,500 32-bit jump address 0000 0000 0000 0000 0010 0111 0001 0000 bits 28-31 from PC+4 Fall 2013, . ELEC 5200-001/6200-001 Lecture 5 17 Datapath for Jump Instruction Branch Jump Branch 4 addr. 1 32 32 Add 32 mux 0 0 mux PC+4 1 4 28 Shift 32 left 2 26 opcode (bits 26-31) 32 Instruction PC to control Address Memory 32 6 Instruction word to control and Fall 2013, . ELEC 5200-001/6200-001 Lecture 5 registers 18 Jump 0-25 Shift 2 left 4 0 mux 1 0 mux Add Branch 0 1 mux opcode ALU MemtoReg 26-31 RegDst CONTROL 21-25 zero MemWrite MemRead Instr. PC mem. 16-20 ALU Reg.File Data 1 mux 0 1 mux 11-15 1 0 mux Combined 0 1 mux mem. Datapaths ALU Sign Shift Cont. 0-15 ext. left 2 0-5 Fall 2013, . ELEC 5200-001/6200-001 Lecture 5 19 Control RegDst Jump Branch MemRead Instruction Control MemtoReg Logic bits 26-31 ALUOp opcode MemWrite ALUSrc RegWrite 2 Instruction ALU to ALU bits 0-5 Control funct. Fall 2013, . ELEC 5200-001/6200-001 Lecture 5 20 Control Logic: Truth Table Inputs: instr. opcode bits Outputs: control signals MemtoReg MemRead MemWrite RegWrite ALOOp1 ALUOp2 ALUSrc RegDst Instr Branch Jump type 31 30 29 28 27 26 R 0 0 0 0 0 0 1 0 0 0 1 0 0 0 1 0 lw 1 0 0 0 1 1 0 0 1 1 1 1 0 0 0 0 sw 1 0 1 0 1 1 X 0 1 X 0 0 1 0 0 0 beq 0 0 0 1 0 0 X 0 0 X 0 0 0 1 0 1 j 0 0 0 0 1 0 X 1 X X 0 X 0 X X X Fall 2013, . ELEC 5200-001/6200-001 Lecture 5 21 How Long Does It Take? Assume control logic is fast and does not affect the critical timing. Major time delay components are ALU, memory read/write, and register read/write. Arithmetic-type (R-type) Fetch (memory read) 2ns Register read 1ns ALU operation 2ns Register write 1ns Total 6ns Fall 2013, . ELEC 5200-001/6200-001 Lecture 5 22 Time for lw and sw (I-Types) ALU (R-type) 6ns Load word (I-type) – Fetch (memory read) 2ns – Register read 1ns – ALU operation 2ns – Get data (mem. Read) 2ns – Register write 1ns – Total 8ns Store word (no register write) 7ns Fall 2013, . ELEC 5200-001/6200-001 Lecture 5 23 Time for beq (I-Type) ALU (R-type) 6ns Load word (I-type) 8ns Store word (I-type) 7ns Branch on equal (I-type) – Fetch (memory read) 2ns – Register read 1ns – ALU operation 2ns – Total 5ns Fall 2013, . ELEC 5200-001/6200-001 Lecture 5 24 Time for Jump (J-Type) ALU (R-type) 6ns Load word (I-type) 8ns Store word (I-type) 7ns Branch on equal (I-type) 5ns Jump (J-type) – Fetch (memory read) 2ns – Total 2ns Fall 2013, . ELEC 5200-001/6200-001 Lecture 5 25 How Fast Can Clock Run? If every instruction is executed in one clock cycle, then: – Clock period must be at least 8ns to perform the longest instruction, i.e., lw. – This is a single cycle machine. – It is slower because many instructions take less than 8ns but are still allowed that much time. Method of speeding up: Use multicycle datapath. Fall 2013, . ELEC 5200-001/6200-001 Lecture 5 26 A Single Cycle Example a31 Delay of 1-bit full adder = 1ns Clock period ≥ 32ns . c32 . 1-b full adder . s31 a2 . a1 1-b full . a0 adder . s2 b31 1-b full s1 . adder s0 . 1-b full . adder b2 b1 Time of adding words ~ 32ns b0 Time of adding bytes ~ 32ns 0 Fall 2013, . ELEC 5200-001/6200-001 Lecture 5 27 A Multicycle Implementation a31 Delay of 1-bit full adder = 1ns . Clock period ≥ 1ns . Time of adding words ~ 32ns Shift a2 Time of adding bytes ~ 8ns a1 a0 1-b full adder b31 s31 . c32 .