c 2016 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes, creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works. DOI: 10.1109/DSD.2016.24 . A. Ablak and I. Damaj, HTCC: Haskell to Handel-C Compiler, The 19th EUROMICRO Conference on Digital System Design, IEEE, Limassol, Cyprus, August 31–September, 2016. P 192–199. https://doi.org/10.1109/DSD.2016.24 HTCC: Haskell to Handel-C Hardware Compiler Ahmed B. Ablak and Issam Damaj Electrical and Computer Engineering Department American University of Kuwait Salmiya, Kuwait Email: fs00015070, [email protected] Abstract—Functional programming languages, such as beyond behavioral VHDL and the other standard tools. The Haskell, enable simple, concise, and correct-by-construction area witnessed the emergence of programming languages and hardware development. HTCC compiles a subset of Haskell to tools such as Handel-C [3], SystemC [4], Matlab HDL Coder, Handel-C language with hardware output. Moreover, HTCC generates VHDL, Verilog, EDIF, and SystemC programs. The LabVIEW, etc. All the modern co-design tools enable the inte- design of HTCC compiler includes lexical, syntax and semantic gration and partitioning of computations into communicating analyzers. HTCC automates a transformational derivation hardware and software subsystems. methodology to rapidly produce hardware that maps onto Field Handel-C is a high-level language with hardware output. Programmable Gate Arrays (FPGAs) . HTCC is generated Handel-C is based on ANSI C; it is extended to the theory of using ANTLR compiler-compiler tool and supports an effective integrated development environment. This paper presents the communication sequential processes (CSP) and the concurrent design rationale and the implementation of HTCC. Several programming language (OCCAM) [5]. Moreover, Handel-C sample generations of first-class and higher-order functions are has the ability to provide both parallel and sequential imple- presented. In-addition, a compilation case-study is presented mentations. Handel-C can target different FPGA types. Recent for the XTEA cipher. The investigation comprises a thorough research effort has been on automating hardware generation evaluation and performance analysis. The targeted FPGAs include Cyclone II, Stratix IV, and Virtex-6 from Altera and to target Handel-C and hardware in general starting from Xilinx. functional specifications, such as, Haskell [6]–[9]. Haskell is a purely functional programming language that I. INTRODUCTION utilizes functions to construct programs. Utilizing Haskell FPGAs are famous and widely used reconfigurable com- functions is presumed to have no side effects, as the eval- puting (RC) systems. FPGAs have become very popular in uation order of the functions is independent [10]. Modern research and industrial applications in different fields, such functional languages are characterized by being strongly typed, arXiv:1907.07764v1 [cs.PL] 10 Jul 2019 as, security, signal processing etc. FPGAs evolved from being concise, clear, lazy, and easy to insure correctness. With no limited in functionality and speed to become high-performance doubt, developing hardware circuits based on the functional processors. Example FPGAs include Stratix from Altera and programming paradigm is a promising and modern topic under Virtex from Xilinx [1], [2]. The flexibility of FPGAs, that are investigation [11]–[13]. Much research effort has been done sometimes described as seas-of-gates, enable the development to benefit from the advantages of functional programming of software paradigms to rapidly reconfigure hardware almost languages in hardware design including Lava [14], Hawk [15], instantly. [16], Hydra [17], HML [18], MHDL [19], DDD system [20], Recently, there has been considerable focus on the devel- SAFL [21], MuFP [22], Ruby [23], and Form [24]. opment of high-level synthesis (HLS) and rapid prototyping HTCC compiles a subset of Haskell to Handel-C, in addi- hardware/software co-design tools. The targets of co-design tion to automatically generating VHDL, Verilog, EDIF, and tools are high design productivity, simplicity, reduced time-to- SystemC. The design of HTCC compiler includes lexical, prototype, correctness, to name a few. Co-design tools include syntax and semantic analyzers. The compiler is generated converting algorithmic behaviors into digital circuits that can using ANTLR based-on a subset of Haskell grammar. HTCC map onto FPGAs. High-level co-design tools are currently Integrated Development Environment (IDE) produces a variety of analysis and schematic files. HTCC successfully connects to external tools, such as, DK Design Suite, Altera Quartus, and ModelSim. The developed compiler targets several FPGA types, and Altera DE2-70 and DE4 FPGA boards. The targeted area of application is cryptography, namely, the XTEA cipher. The paper is organized so that Section II presents the rapid prototyping methodology adopted by HTCC. Section III details the HTCC construction including the compiler and IDE designs. The compiler implementation is presented in Section IV. Sections V and VI present the compilation approach of first-class and higher-order functions and a case-study from cryptography. A thorough analysis and evaluation is presented in Section VII. Section VIII concludes the paper and sets the ground for future works. Fig. 1. The transformational derivation and refinement methodology. II. BACKGROUND HTCC adopts the transformational derivation and refine- process Store stores a communication construct in a simple or ment methodology of Abdallah et. al [8], [25]. The adopted composite variable [9]. methodology refines functional specifications into parallel The methodology also supports a rich set of refined higher- hardware implementations in Handel-C. Several case-studies order functions, such as, map, zip, zipwith, etc. The refinement for the methodology were carried out by Damaj et. al [9], [26]– of higher-order functions to processes could be done in stream [28], however the implementations did not include a compiler or vector settings, or a combination of them. In Handel-C, that automates the refinement procedure. datatypes are refined to structures (struct), while processes Figure 1 depicts the step-wise refinement procedure, where are refined to macro procedures [9]. Handel-C compiler gen- functional specifications are refined to hardware. The adopted erates the required hardware circuits that can be mapped onto methodology is systematic in the sense that it is carried out FPGAs. using the following step-by-step procedure: • Specify the algorithm in a functional setting relying on III. COMPILER CONSTRUCTION higher-order functions as the main building constructs HTCC is a compiler that automates the presented refinement wherever necessary. methodology. The presented version of HTCC Integrated De- • Apply the predefined set of rules to create the corre- velopment Environment (IDE) supports the following: sponding CSP networks according to a chosen degree of • Compiles a subset of Haskell to Handel-C parallelism. • Automatically connects to the DK Design Suite from • Write the equivalent Handel-C code and complete the Mentor Graphics to run the Handel-C Compiler; it ver- hardware compilation. ifies, generates, and analyzes the corresponding VHDL, The refinement steps are aided by different compilers and Verilog, EDIF, or SystemC code integrated development environments. HTCC automates the • Automatically connects to Glasgow Haskell Compiler development process including the background run of exist- (GHC) to run and test the Haskell code ing FPGA vendor interfaces and Haskell, Handel-C, VHDL, • Automatically connects to Altera Quartus II to run, test, Verilog, EDIF, and SystemC compilers. analyze hardware designs; place and route; produce bit The adopted methodology refines both datatypes and func- files; and target specific FPGAs and FPGA boards. tions. Datatypes are refined to Items, Streams, and Vectors to • Provides an easy-to-use, rich, and modern development create communicating entities based-on the message passing environment technique. The Item corresponds to a basic type, such as an Integer data type , and it is to be communicated on a single A. Compiler Design using ANTLR communicating channel. The Stream is a purely sequential HTCC is developed using the compiler-compiler tool method of communicating a list of values. The Vector is a ANTLR. ANTLR provides an easy-to-use compiler construc- refinement of a simple list of items that communicates the tion structure; ANTLR is efficient, reliable, and effective [26]. entire structure in parallel [9]. ANTLR uses an adaptive parsing technique that provides In addition, the methodology refines functions to commu- runtime grammar analysis [29]. Moreover, ANTLR uses the nicating processes. The refinement comprises a library of Extended BackusNaur Form (EBNF). The efficiency and ef- standard processes, such as, Produce and Store that aid the fectiveness of utilizing ANTLR is primarily due to its ability to communication of refined datatypes. The Produce process is support direct left-recursion, side-effecting actions (mutators) used to produce values on the channels of a certain commu- and predictions from the corresponding grammar [30]. nication construct (Item, Stream, Vector, etc.). These values