University of Alberta PARALLELFACLT SISICLATIOS ON THE CeRAhI ~\RCHITECTCRE -. & 'w' Albert L.C. Kwong -4 thesis submitted to the Faculty of Graduate Studies and Research in partial fulfill- ment of the requirements for the degree of Master of Science. Depart ment of Elect rical and Corn put er Engineering Edmonton. ,Alberta Fa11 1998 National Library Bibliothèque nationale du Canada Acquisitions and Acquisitions et Bibliographie Services services bibliographiques 395 Weaington Street 395, nie Wellington OttawaON K1AW ûüawaON K1AW canada canada The author has granted a non- L'auteur a accordé une licence non exclusive licence allowing the exclusive permettant à la National Libracy of Canada to Bibiiothèque nationale du Canada de reproduce, loan, distriiute or sell reproduire, prêter, distxibuer ou copies of this thesis in microform, vendre des copies de cette thèse sous paper or electronic formats. la fome de microfïche/nlm, de reproduction sur papier ou sur format électronique. The author retains ownership of the L'auteur conserve la propriété du copyright in this thesis. Neither the droit d'auteur qui protège cette thèse. thesis nor substantid extracts fiom it Ni la thèse ni des extraits substantiels may be printed or otherwise de celle-ci ne doivent être imprimés reproduced without the author's ou autrement reproduits sans son permission. autorisation. Abstract Fault simulation is used to determine if the faulty behal-iour of a given circuit with a fault added is detectable ii-hen a list of test patterns is supplied. Siniulating al1 potential faults in a circuit witli a sufficient number of patterns to observe a11 faiilts is comput at ionall>-intensive. Fort unately. a tiigh degree of parallelism esistc in the fault simuiat ion application. For esample. convent ional parallel faul t simulat ion can t îke adlantage of the datapat h of the processor and use the logical operations provided by the CPIl to perform parallel gate evaluations. This algorit lin1 cari he furt her accelerated usirig a niassii-ely parallel coniputer. C'.R.-\.\I is a S [.\ID architecture t hat integrates processing elements \vit h rnemorj-. -4 SJ-steriiwith 2.5611 bytes of C.R.-\.\I rnemory can contain up to 12Sk processing elenient s i PE). providing a ver!- wide datapat 11. \\ë trislied to deterniirie \diet lier or not a parallel fault siniuiator impleriiented on C'.R.-\.\I coiilcl niake effective use of ttiis datapat h to accelerate fault simulatioii. In t liis research. three different esperimental C'eR.-\II fault siniulators lvere de- signed. The simulators implement pat tern-parallel fault sirnulat ion ( sirn/-pp). fault- parallel fault simulation (sincf-h~s).and a hybrid of the pattern-parallel and fault- parallel algorithnis (sirilf-hps). T~voversions of sirrljXps were iiiipleiiiented: static- hjvbrid parallel fault simulation and dynamic-hybrid parallel fault simiilation. Bx using the ISC.-\S B5 benchmark circuits to e\-aluate the siniulators. it was found that al1 of Our sirnulators (escept simf-Jpa) run faster thri our benchmark conventional siniulator. sirr?f. SitnI-fps is geiierally inefficient. escept for circuits ivith rnostl! eaq--to-detect faults. Sirnf-pps is not as efficient as tlie liybricl fault siiiiiilators in niost of the cases. escept when the circuit has many hard-tedetect faults. \\'lien sirniilating with 4096 PEs. the hl-brid faolt simulators were found to irnproi-e upori our benchmark simulator b~-10 to 30 tinies. The h>-brid fault siniulator is scalable in that we observe increasing speed-up for up to 1Gk PEs. Acknowledgement s 1 would Iike to thank m>-supervisors. Dr. Bruce F. Cockburn and Dr. Duncan C. Elliott . for t heir help in the course of this research. The? have provicled valuable ideas and background knowledge. I \vould also like to thank my supervisory committee. Dr. Martin llargala and Dr. Jonathan Schaeffer. who have gi\-en me many useful comments. My thanks also goes to TRLabs and lkronet for their financiai support. Most importantly. 1 thank C;od who gave me this opportunity to study and the ability to finish it. Praise the Lord. Amen. Contents 1 Introduction 1 1.1 ProblernDefinition ............................ 1 1.2 Testing and Fauit Simulation ...................... -1- 1-13 SIlID Parallel .Architectures ....................... 4 . 4 Thesis Outline ............................... 3 2 CeRAM and SIMD machines 7 . 2.1 Historj. ................................... 1 2.2 The C'oRAlI Architectirre ........................ 10 2.2. I Tlie Processing Ele~nent( PE i .................. 11 2.2.- The C'oinnliinicat ion Setwork .................. 12 2.3 llernory St riictirre ........................ 14 2.3 The CaR.-\II Programniing Ilotlel .................... 1-1 2.4 .-\ci i.antagesantl Disad\antagesofC0oR.4.\I ............... 17 3 Fault Models 19 3 . L Introdiict ion ................................ 19 3.2 Strick..-lt Faults .............................. 20 3 ..3 Gate-Delay Faiilts ............................. -1.--1 3.4 Stuck-Open Faults ............................ 2.5 4.5 Fault Inipiication and Eqitii-alence Among Fault .\ Iotlels ....... -1- 4 Fault Simulation 36 3.1 Int rodiict ion ................................ 36 4.2 Seqiient ial Faiilt Simtilation ....................... 40 8 Hybrid Fault Simulation on CaRAM 103 S .1 Overview .................................. 103 8.2 Design Details ............................... 105 Y 2.1 Partit ioning CORAM hlemory .................. 10.5 Y 2.2 llodified Fault-Farnily Fault Simulation ............. 109 8.2.3 Hybrid-Parallel Fault Simulation ................ 112 S.2.4 Fault Triggering and Fault Detection .............. 113 8.2.5 Dynamic-HJ-brid Fault Simulation ................ 119 S .3 Evaluation ................................. 118 s.3.1 PE Ctilization ........................... 1'21 S.3.2 Simulating I-sing a Larger CeR.-\.\I ............... 125 9 Conclusion 128 9.1 Summaryof Results ........................... ES 9.2 Furt her Research ............................. 130 9.2.1 Fauit-Simulating Large Circuits ................. 131 9.2.2 ÇequentialCircuits ........................ 131 92.3 Other Fault ,\ loclels ........................ 133 Bi bliography 133 Appendices 136 -4 Source Code 136 1 Basic lioduies ............................... 1:36 structure-h ............................. 136 prototype-h ............................ 137 simf.C ............................... 137 readiscas.Cg ............................ 1:38 genfau1t.C ............................ 111 fault lamil'.. C ........................... 135 heap-h ............................... 116 heap.C ............................... 117 4-19 crammapper.h .......................... 14s A .1.10 crammapper-C .......................... 118 A.2 sirnf Benchmark Fault Simulator ..................... 150 A.3 Pat tern-Parallel Fault Simulator ..................... 1.36 .=\.a Fault-Parallel Fault Sirnulator ...................... 161 4.5 Hybrid Fault Simulator .......................... 166 List of Tables :3.I Triggering Conditions for Stuck-At Faults affecting SOT Gates (In- verters) .................................. 3.2 Triggering Conditions of Stuck-At Faults for '-input SASD Gate . 3.3 Triggering Conditions for Gate-Delay Faults Affecting a ?-input SAXD Gate .................................... 3.4 Triggering Conditions for St uck-Open Faults -4ffect ing 2-input ;\XII Gate .................................... 3.5 Triggering Conditions for Faults Affecting the SOT Gate ....... 3.6 Triggering Conditions for Faults .A ffecting the BCFF Gate ...... 3.7 Triggeriiig Condition for Faulti -4ffectinj the S.-Il-D Gate ...... 3- Triggering Conditions for Faults Affecting the ASD Gate ....... 3.9 Trigering Conditions for Faults -4ffecting the TOR Gate ....... 3.10 Triggering Conditions for Faults Affecting the OR Gate ........ 5 1 Root-to-Fault Ratio for the ISC.4SS.j Circuits ............. 5.2 Evaluar ion of Simulation Speed (in seconds) .............. 5.3 Fault C'ollapsing Results for the ISC-AS85 Circuits ........... 6.1 Comparing simj and simf-pps in Terms of Speed- L-p .......... 6.2 C'omparison of PE L*t ilization for simf and simflpps .......... I -1 Speed Difference in Fault-Free Simulation ................ 7.2 llemory Requirernent \Vit h or \Vit hour Dynamic .\ lernory -4llocation 7.3 Interpretation of Flags in the Event-List ................ t -4 Result Cornparison of PPS with FPS .................. .. t 3 Ana1pis of the FauIt-ParalleI FauIr Simulation Results ........ PE 1-tilization : Average Xurnber of FFs Sirnulatecl Per Pass ..... 99 Effect of Depth-First-Search from Output Optimization ........ 100 Fault Triggering Detection Time in FPS ................ 101 Speeding-up HPS by L-sing Depth-First-Search Grouping ....... 110 Speeding-up HPS by king C*R.UI Mapper .............. 112 Final Results ............................... 118 PE rtilizations of the Hybrid Fault Simiilators ............. 123 Fauit Simulation Resuits with 41; PEs ................. 125 Speed-up of Fault Simulations Going frorn 11; PEs to 41; PEa .... 12.5 Optimization Implementedin Each Fault Simulator .......... 129 Fault Simulation Results \\'ith 41; PEs Running at 143.\IHz ..... 130 List of Figures . SISD .Single Instruction Stream . Single Data Stream ......... t SIAID .Single Instruction Stream . AIuitiple Data Stream ....... 8 11ND . Mdtiple Instruction Stream. SIuItiple Data Stream . 9 The CaRA,\ 1 Architecture ........................ 10 C'OR-UIPEStructure .......................... 11 CeR.411 Programming llodels .....................