Embedded Design Handbook Subscribe EDH | 2018.11.12 Send Feedback Latest document on the web: PDF | HTML Contents Contents 1. Introduction................................................................................................................... 6 1.1. Document Revision History for Embedded Design Handbook........................................ 6 2. First Time Designer's Guide............................................................................................ 8 2.1. FPGAs and Soft-Core Processors.............................................................................. 8 2.2. Embedded System Design...................................................................................... 9 2.3. Embedded Design Resources................................................................................. 11 2.3.1. Intel Embedded Support........................................................................... 11 2.3.2. Intel Embedded Training........................................................................... 11 2.3.3. Intel Embedded Documentation................................................................. 12 2.3.4. Third Party Intellectual Property.................................................................12 2.4. Intel Embedded Glossary...................................................................................... 13 2.5. First Time Designer's Guide Revision History............................................................14 3. Hardware System Design with Intel Quartus Prime and Platform Designer.................. 15 3.1. FPGA Hardware Design......................................................................................... 16 3.1.1. Connecting Your FPGA Design to Your Hardware...........................................17 3.1.2. Connecting Signals to your Platform Designer System...................................17 3.1.3. Constraining Your FPGA-Based Design.........................................................18 3.2. System Design with Platform Designer....................................................................19 3.2.1. Intel System on a Programmable Chip (Platform Designer) Solutions.............. 20 3.2.2. Platform Designer Design..........................................................................22 3.3. Interfacing an External Processor to an Intel FPGA................................................... 23 3.3.1. Configuration Options............................................................................... 24 3.3.2. RapidIO Interface.....................................................................................27 3.3.3. PCI Express Interface............................................................................... 29 3.3.4. PCI Interface...........................................................................................31 3.3.5. Serial Protocol Interface (SPI)................................................................... 31 3.3.6. Custom Bridge Interfaces..........................................................................33 3.4. Avalon-MM Byte Ordering......................................................................................35 3.4.1. Endianness............................................................................................. 35 3.4.2. Avalon-MM Interface Ordering................................................................... 36 3.4.3. Nios II Processor Data Accesses.................................................................40 3.4.4. Adapting Processor Masters to be Avalon-MM Compliant................................42 3.4.5. System-Wide Design Recommendations...................................................... 50 3.5. Memory System Design........................................................................................ 52 3.5.1. Memory Types......................................................................................... 52 3.5.2. On-Chip Memory......................................................................................52 3.5.3. External SRAM.........................................................................................55 3.5.4. Flash Memory..........................................................................................56 3.5.5. SDRAM...................................................................................................58 3.5.6. Case Study............................................................................................. 64 3.6. Nios II Hardware Development Tutorial................................................................... 68 3.6.1. Software and Hardware Requirements........................................................ 68 3.6.2. Intel FPGA IP Evaluation Mode................................................................... 69 3.6.3. Nios II Design Example.............................................................................69 3.6.4. Nios II System Development Flow.............................................................. 71 3.6.5. Creating the Design Example.....................................................................75 Embedded Design Handbook Send Feedback 2 Contents 3.7. Platform Designer System Design Tutorial............................................................... 89 3.7.1. Software and Hardware Requirements........................................................ 90 3.7.2. Download and Install the Tutorial Design Files..............................................91 3.7.3. Open the Tutorial Project...........................................................................91 3.7.4. Creating Platform Designer Systems...........................................................92 3.7.5. Assemble a Hierarchical System............................................................... 100 3.7.6. Viewing the Memory Tester System in Platform Designer............................. 107 3.7.7. Compiling and Downloading Software to a Development Board.....................107 3.7.8. Debugging Your Design........................................................................... 109 3.7.9. Verifying Hardware in System Console...................................................... 109 3.7.10. Simulating Custom Components............................................................. 111 3.7.11. View a Diagram of the Completed System................................................117 3.8. Hardware System Design with Intel Quartus Prime and Platform Designer Revision History...........................................................................................................118 4. Software System Design with a Nios II Processor ......................................................119 4.1. Nios II Command-Line Tools................................................................................ 120 4.1.1. Intel Command-Line Tools for Board Bringup and Diagnostics.......................120 4.1.2. Intel Command-Line Tools for Flash Programming.......................................122 4.1.3. Intel Command-Line Tools for Software Development and Debug..................125 4.1.4. Intel Command-Line Nios II Software Build Tools........................................128 4.1.5. Rebuilding Software from the Command Line............................................. 129 4.1.6. GNU Command-Line Tools....................................................................... 130 4.2. Developing Nios II Software................................................................................ 137 4.2.1. Software Development Cycle................................................................... 138 4.2.2. Software Project Mechanics..................................................................... 142 4.2.3. Developing With the Hardware Abstraction Layer........................................161 4.2.4. Linking Applications................................................................................182 4.3. Nios II MPU Usage..............................................................................................184 4.3.1. Requirements........................................................................................ 184 4.3.2. General Usage....................................................................................... 185 4.3.3. Nios II MPU Design Examples...................................................................195 4.4. Profiling Nios II Systems..................................................................................... 200 4.4.1. Requirements........................................................................................ 200 4.4.2. Tools.................................................................................................... 200 4.4.3. Using the GNU Profiler to Measure Code Performance..................................202 4.4.4. Using Performance Counter and Timer Components.................................... 209 4.4.5. Troubleshooting..................................................................................... 215 4.5. Software System Design with a Nios II Processor Revision History............................ 216 5. Nios II Configuration and Booting Solutions............................................................... 217 5.1. Introduction...................................................................................................... 217 5.1.1. Prerequisites......................................................................................... 217 5.2. Nios II Processor Booting Methods........................................................................218