ADVANCED AUDIO CODING ON AN FPGA By Ryan Linneman School of Information Technology and Electrical Engineering, University of Queensland, Brisbane. Submitted for the Degree of Bachelor of Engineering (Honours) in the division of Computer Systems Engineering October 2002 i ii Cromwell College W alcott St. St. Lucia QLD 4067 16 October 2002 Professor Simon Kaplan Head of School of Information Technology and Electrical Engineering University of Queensland St. Lucia, QLD 4072 Dear Professor Kaplan, In accordance with the requirements of the Degree of Bachelor of Engineering (Honours) in the division of Computer Systems Engineering, I present the following thesis entitled —Advanced Audio Coding on an FPGA“. This work was performed under the supervision of Dr Peter Sutton. I declare that the work in this thesis is written with honesty and integrity, and is a true report of the work I have undertaken. The work submitted is my own, except as acknowledged, and has not previously been submitted for a degree at The University of Queensland or any other institution. Yours sincerely, Ryan Linneman i ii iv Abstract This thesis presents an investigation and partial implementation of the MPEG-2 AAC decoding algorithm on a Field Programmable Gate Array (FPGA). Advanced Audio Coding (AAC) is a state-of-the-art natural audio coding algorithm that is superior to MP3 and is capable of producing better than CD quality audio. The algorithm incorporates a number of decoding tools, most of which involve heavily repetitive computations. An official AAC conformance test bitstream was selected for decoding, and five of the ten decoding tools are required to decode the bitstream. An in-depth analysis and partial decoding of the bitstream was undertaken and the results provide the theoretical foundation for the thesis. The hardware environment for the thesis was a Xess XSV Development board housing a Virtex XCV300 FPGA. The FPGA‘s capacity to handle parallel processing and to perform well with repetitive tasks suited it well to the AAC decoding algorithm. An full implementation of the quantisation and scalefactor tools using fixed-point arithmetic was written in VHDL and a partial implementation of the bitstream demultiplexer was also written. The quantisation and scalefactor tools were synthesised and implemented with Xilinx Foundation and when executed on the FPGA, showed ê1% accuracy compared to a floating-point software implementation. Recommendations for future work and development for the MPEG-2 AAC algorithm on an FPGA are made also. v vi Acknowledgements This thesis could not have been completed without the guidance and encouragement of many people. I would like to particularly acknowledge those below. Dr Peter Sutton for his supervision and guidance throughout the project and his commitment to meeting with me each week to encourage me and to offer me feedback. Simon Leung, for his help with the VHDL implementation and taking the time to respond to my bothersome emails. My M um and Dad for their continual encouragement and their wonderful parenting over 21 years to put me in a place to write this thesis. My friends at Cromwell, especially M el Stuart, for sharing the load. v ii viii Contents Abstract............................................................................................................................v Acknowledgements........................................................................................................vii Contents ..........................................................................................................................ix List of Figures................................................................................................................xii List of Tables ...............................................................................................................xiii 1 INTRODUCTION...................................................................................................1 1.1 THE INTERNET AUDIO MARKET .........................................................................1 1.2 THE AAC STANDARD ISO/IEC 13818-7 ...........................................................2 1.3 OBJECTIVES AND CONTRIBUTION.......................................................................4 1.4 OVERVIEW OF REMAINING CHAPTERS.................................................................5 2 REVIEW OF PREVIOUS W ORK........................................................................6 2.1 MP3 FPGA SOLUTIONS.....................................................................................6 2.2 LICENSED AAC DECODERS ................................................................................7 2.2.1 Texas Instruments..........................................................................................7 2.2.2 Princeton.......................................................................................................7 2.2.3 Cirrus............................................................................................................7 2.2.4 Micronas GmbH............................................................................................8 2.2.5 ARM MOVETM Technology Audio Components............................................8 2.2.6 Comparison and Conclusion.........................................................................8 2.3 RESEARCH PUBLICATIONS AND IMPLEMENTATIONS ...........................................8 2.4 COMPARISON OF DSP W ITH FPGA ....................................................................9 2.5 SOFTW ARE IMPLEMENTATIONS ........................................................................11 2.6 SUMMARY........................................................................................................12 3 M PEG-2 AAC DECODING ALGORITHM ......................................................13 3.1 OVERVIEW OF THE MPEG-2 AAC DECODING ALGORITHM ............................13 3.2 ISO/IEC 13818-7 AUDIO TEST BITSTREAMS...................................................17 3.3 EXTRAPOLATION OF BLOCK DIAGRAM ............................................................17 3.4 SUMMARY........................................................................................................18 4 A CASE STUDY: ”L1_fs_mod‘...........................................................................19 4.1 DECODING THE HEADER ...................................................................................19 4.2 DECODING <DSE>...........................................................................................21 4.3 DECODING <SCE>...........................................................................................21 4.3.1 Decoding ics_info().....................................................................................21 4.3.2 Decoding section_data().............................................................................24 4.3.3 Decoding scale_factor_data().....................................................................25 4.3.4 Decoding spectral_data()............................................................................27 4.4 DECODING <FIL>............................................................................................27 4.5 DECODING <TERM>.......................................................................................28 4.6 NOISELESS CODING..........................................................................................28 4.7 QUANTISATION ................................................................................................29 4.8 SCALEFACTORS ................................................................................................30 4.9 FILTER BANK ...................................................................................................30 ix 4.10 SUMMARY .......................................................................................................32 5 HARDW ARE ENVIRONM ENT........................................................................33 5.1 XILINX XCV300 FPGA ..................................................................................33 5.2 AK4520A STEREO CODEC ...............................................................................33 5.3 XC95108 CPLD .............................................................................................34 5.4 VHDL AND ACTIVE-HDL...............................................................................34 5.5 XILINX FOUNDATION.......................................................................................35 5.6 XSTOOLS ........................................................................................................36 5.7 SUMMARY .......................................................................................................37 6 ALGORITHM IM PLEM ENTATION...............................................................38 6.1 BITSTREAM DEMULTIPLEXER..........................................................................38 6.1.1 The header.................................................................................................. 40 6.1.2 <DSE> ....................................................................................................... 40 6.1.3 <SCE>........................................................................................................ 41 6.1.4 <FIL> and <TERM>................................................................................. 44 6.2 NOISELESS CODING .........................................................................................44