Alpha 21264/EV6 Microprocessor Hardware Reference Manual Order Number: DS–0027C–TE This manual is directly derived from the internal 21264/EV6 Specifications, Revi- sion 4.5. You can access this hardware reference manual in PDF format from the following site: ftp://ftp.compaq.com/pub/products/alphaCPUdocs Revision/Update Information: This is a revised document. It supercedes the Alpha 21264 Microprocessor Hardware Reference Manual (DS–0027B–TE). Compaq Computer Corporation Shrewsbury, Massachusetts March 2002 The information in this publication is subject to change without notice. COMPAQ COMPUTER CORPORATION SHALL NOT BE LIABLE FOR TECHNICAL OR EDITORIAL ERRORS OR OMISSIONS CONTAINED HEREIN, NOR FOR INCIDENTAL OR CONSEQUENTIAL DAM- AGES RESULTING FROM THE FURNISHING, PERFORMANCE, OR USE OF THIS MATERIAL. THIS INFORMATION IS PROVIDED “AS IS” AND COMPAQ COMPUTER CORPORATION DISCLAIMS ANY WARRANTIES, EXPRESS, IMPLIED OR STATUTORY AND EXPRESSLY DISCLAIMS THE IMPLIED WAR- RANTIES OF MERCHANTABILITY, FITNESS FOR PARTICULAR PURPOSE, GOOD TITLE AND AGAINST INFRINGEMENT. This publication contains information protected by copyright. No part of this publication may be photocopied or reproduced in any form without prior written consent from Compaq Computer Corporation. © Compaq Computer Corporation 2002. All rights reserved. Printed in the U.S.A. COMPAQ, the Compaq logo, the Digital logo, and VAX Registered in United States Patent and Trademark Office. Pentium is a registered trademark of Intel Corporation. Other product names mentioned herein may be trademarks and/or registered trademarks of their respective compa- nies. Alpha 21264/EV6 Hardware Reference Manual Table of Contents Preface 1 Introduction 1.1 TheArchitecture.......................................................... 1–1 1.1.1 Addressing........................................................... 1–2 1.1.2 Integer Data Types. .................................................. 1–2 1.1.3 Floating-PointDataTypes............................................... 1–2 1.2 21264/EV6 Microprocessor Features .......................................... 1–3 2 Internal Architecture 2.1 21264/EV6 Microarchitecture ................................................ 2–1 2.1.1 InstructionFetch,Issue,andRetireUnit.................................... 2–2 2.1.1.1 Virtual Program Counter Logic . ...................................... 2–2 2.1.1.2 BranchPredictor................................................... 2–3 2.1.1.3 Instruction-StreamTranslationBuffer................................... 2–5 2.1.1.4 InstructionFetchLogic.............................................. 2–5 2.1.1.5 RegisterRenameMaps............................................. 2–6 2.1.1.6 Integer Issue Queue ................................................ 2–6 2.1.1.7 Floating-Point Issue Queue .......................................... 2–7 2.1.1.8 Exception and Interrupt Logic . ...................................... 2–8 2.1.1.9 Retire Logic....................................................... 2–8 2.1.2 Integer Execution Unit .................................................. 2–8 2.1.3 Floating-PointExecutionUnit............................................. 2–10 2.1.4 ExternalCacheandSystemInterfaceUnit.................................. 2–11 2.1.4.1 VictimAddressFileandVictimDataFile................................ 2–11 2.1.4.2 I/OWriteBuffer.................................................... 2–11 2.1.4.3 Probe Queue...................................................... 2–11 2.1.4.4 DuplicateDcacheTagArray.......................................... 2–11 2.1.5 OnchipCaches........................................................ 2–11 2.1.5.1 InstructionCache.................................................. 2–11 2.1.5.2 DataCache....................................................... 2–12 2.1.6 MemoryReferenceUnit................................................. 2–12 2.1.6.1 LoadQueue...................................................... 2–13 2.1.6.2 StoreQueue...................................................... 2–13 2.1.6.3 MissAddressFile.................................................. 2–13 2.1.6.4 DstreamTranslationBuffer........................................... 2–13 2.1.7 SROMInterface....................................................... 2–13 2.2 PipelineOrganization...................................................... 2–13 2.2.1 PipelineAborts........................................................ 2–16 2.3 InstructionIssueRules..................................................... 2–16 Alpha 21264/EV6 Hardware Reference Manual iii 2.3.1 InstructionGroupDefinitions............................................. 2–17 2.3.2 EboxSlotting......................................................... 2–18 2.3.3 InstructionLatencies................................................... 2–19 2.4 InstructionRetireRules..................................................... 2–21 2.4.1 Floating-PointDivide/SquareRootEarlyRetire............................... 2–21 2.5 RetireofOperateInstructionsintoR31/F31..................................... 2–22 2.6 LoadInstructionstoR31andF31............................................. 2–22 2.6.1 NormalPrefetch:LDBU,LDF,LDG,LDL,LDT,LDWU,HW_LDLInstructions....... 2–23 2.6.2 PrefetchwithModifyIntent:LDSInstruction................................. 2–23 2.6.3 Prefetch,EvictNext:LDQandHW_LDQInstructions.......................... 2–23 2.6.4 Prefetch with the LDx_L / STx_C Instruction Sequence . ...................... 2–23 2.7 SpecialCasesofAlphaInstructionExecution.................................... 2–23 2.7.1 LoadHitSpeculation................................................... 2–24 2.7.2 Floating-PointStoreInstructions.......................................... 2–25 2.7.3 CMOVInstruction...................................................... 2–26 2.8 MemoryandI/OAddressSpaceInstructions.................................... 2–26 2.8.1 MemoryAddressSpaceLoadInstructions.................................. 2–27 2.8.2 I/O Address Space Load Instructions. ...................................... 2–27 2.8.3 MemoryAddressSpaceStoreInstructions.................................. 2–28 2.8.4 I/OAddressSpaceStoreInstructions...................................... 2–28 2.9 MAFMemoryAddressSpaceMergingRules.................................... 2–29 2.10 InstructionOrdering........................................................ 2–30 2.11 ReplayTraps............................................................. 2–31 2.11.1 MboxOrderTraps..................................................... 2–31 2.11.1.1 Load-LoadOrderTrap.............................................. 2–31 2.11.1.2 Store-LoadOrderTrap.............................................. 2–31 2.11.2 OtherMboxReplayTraps............................................... 2–31 2.12 I/OWriteBufferandtheWMBInstruction....................................... 2–32 2.12.1 MemoryBarrier(MB/WMB/TBFillFlow).................................... 2–32 2.12.1.1 MBInstructionProcessing........................................... 2–32 2.12.1.2 WMBInstructionProcessing.......................................... 2–33 2.12.1.3 TBFillFlow....................................................... 2–33 2.13 Performance Measurement Support—Performance Counters . ...................... 2–35 2.14 Floating-PointControlRegister............................................... 2–35 2.15 AMASKandIMPLVERValues............................................... 2–37 2.15.1 AMASK.............................................................. 2–37 2.15.2 IMPLVER............................................................ 2–38 2.16 DesignExamples......................................................... 2–38 3 Hardware Interface 3.1 21264/EV6 Microprocessor Logic Symbol ...................................... 3–1 3.2 21264/EV6 Signal Names and Functions . ...................................... 3–3 3.3 PinAssignments.......................................................... 3–8 3.4 MechanicalSpecifications................................................... 3–18 3.5 21264/EV6 Packaging...................................................... 3–19 4 Cache and External Interfaces 4.1 IntroductiontotheExternalInterfaces.......................................... 4–1 4.1.1 SystemInterface...................................................... 4–3 4.1.1.1 CommandsandAddresses........................................... 4–4 4.1.2 Second-Level Cache (Bcache) Interface . ................................. 4–4 4.2 PhysicalAddressConsiderations............................................. 4–4 4.3 BcacheStructure.......................................................... 4–6 4.3.1 Bcache Interface Signals ................................................ 4–7 iv Alpha 21264/EV6 Hardware Reference Manual 4.3.2 SystemDuplicateTagStores............................................. 4–7 4.4 VictimDataBuffer......................................................... 4–8 4.5 Cache Coherency . ....................................................... 4–8 4.5.1 Cache Coherency Basics................................................ 4–8 4.5.2 CacheBlockStates.................................................... 4–9 4.5.3 CacheBlockStateTransitions............................................ 4–10 4.5.4 UsingSysDcCommands................................................ 4–11 4.5.5 DcacheStatesandDuplicateTags........................................ 4–14 4.6 LockMechanism.......................................................... 4–14 4.6.1 In-OrderProcessingofLDx_L/STx_CInstructions...........................