Appendix 1: 6800 Instruction Set Store Reference Instructions ADDRESS MODES OPERATION MNEMONIC Immediate Direct Indexed Extended Add to A ADDA 8B 9B AB BB Add to B ADDB CB DB EB FB Add to A + Carry ADCA 89 99 A9 B9 Add to B + Carry ADCB C9 D9 E9 F9 AND with A ANDA 84 94 A4 B4 AND with B ANDB C4 D4 E4 F4 Bit test with A BITA 85 95 AS BS Bit test with B BITB CS D5 ES FS Clear CLR 6F 7F Compare with A CMPA 81 91 Al Bl Compare with B CMPB C1 D1 El F1 Complement (1 's) COM 63 73 Decrement DEC 6A 7A Exc1us. OR with A EORA 88 98 A8 B8 Exc1us. OR with B EORB C8 D8 E8 F8 Increment INC 6C 7C Load Acc.A LDAA 86 96 A6 B6 Load Acc. B LDAB C6 D6 E6 F6 OR with A ORAA 8A 9A AA BA OR with B ORAB CA DA EA FA Rotate Left ROL 69 79 Rotate Right ROR 66 76 Shift Left, Arith. ASL 68 78 Shift Right, Arith. ASR 67 77 Shift Right, Logic LSR 64 74 Store Acc. A STAA 97 A7 B7 Store Acc. B STAB D7 E7 F7 Subtract from A SUBA 80 90 AO BO Subtract from B SUBB CO DO EO FO 138 Appendix 1: 6800 Instruction Set 139 Sub. from A with Carry SBCA 82 92 A2 B2 Sub. from B with Carry SBCB C2 D2 E2 F2 Test TST 6D 7D Compare Index Reg. CPX 8C 9C AC BC Load Index Reg. LDX CE DE EE FE Load Stack Pointer LDS 8E 9E AE BE Store Index Reg. STX DF EF FF Store Stack Pointer STS 9F AF BF Implicitly Addressed Instructions OPERATION MNEMONIC CODE Add Accumulators ABA IB Clear Acc. A CLRA 4F Clear Acc. B CLRB SF Compare Accumulators CBA 11 Complement Acc. A COMA 43 Complement Acc. B COMB 53 Negate Acc. A NEGA 40 Negate Acc. B NEGB 50 Decimal Adjust Acc. A DAA 19 Decrement Acc. A DECA 4A Decrement Acc. B DECB SA Increment Acc. A INCA 4C Increment Acc. B INCB 5C Push from Acc. A PSHA 36 Push from Acc. B PSHB 37 Pull to Acc. A PULA 32 Pull to Acc. B PULB 33 Rotate Left Acc. A ROLA 49 Rotate Left Acc. B ROLB 59 Arith. Shift Left Acc. A ASLA 48 Arith. Shift Left Acc. B ASLB 58 Arith. Shift Right Acc. A ASRA 47 Arith. Shift Right Acc. B ASRB 57 Logic Shift Right Acc. A LSRA 44 Logic Shift Right Acc. B LSRB 54 Subtract Accumulators SBA 10 Transfer Accumulators A to B TAB 16 Transfer Accumulators B to A TBA 17 Test Acc. A TSTA 4D 140 An Introduction to Low Level Programming for MicroDrocessors Test Acc. B TSTB SD Decrement Index Reg. DEX 09 Decrement Stack Pointer DES 34 Increment Index Reg. INX 08 Increment Stack Pointer INS 31 Transfer IR to SP TXS 3S Transfer SP to IR TSX 31 Clear Carry Bit CLC OC Clear Interrupt Mask CLI OE Clear Overflow Bit CLV OA Set Carry Bit SEC OD Set Interrupt Mask SEI OF Set Overflow Bit SEV OB Transfer Acc. A to CC Reg. TAP 06 Transfer CC Reg. to Acc. A TPA 07 Branch Instructions - Relative Addressing OPERATION MNEMONIC conE Branch Always BRA 20 Branch if Carry Clear BCC 24 Branch if Carry Set BCS 2S Branch if = Zero BEQ 27 Branch if ~ Zero BGE 2C Branch if> Zero BGT 2E Branch if Higher BHI 22 Branch if ~ Zero BLE 2F Branch if Lower or Same BLS 23 Branch if Minus BMI 2B Branch if Not = Zero BNE 26 Branch if Overflow Clear BVC 28 Branch if Overflow Set BVS 29 Branch if Plus BPL 2A Branch to Subroutine BSR 8D Appendix 1: 6800 Instruction Set 141 Jump and Return Instructions ADDRESS MODES OPERATION MNEMONIC Indexed Extended Implicit Jump JMP 6E 7E Jump to Subroutine JSR AD BD No Operation NOP 01 Return from Interrupt RTI 3B Return from Subroutine RTS 39 Software Interrupt SWI 3F Wait for Interrupt WAI 3E Appendix 2: Z80 Instruction Set 8-bit Load Operations SOURCE Register Register Indirect Indexed Immed. A B C D E H L (HL) (BC) (DE) X Y 4 7F 78 79 7A 7B 7C 7D 7E OA lA DD7E F07E 3£ D R B 47 40 41 42 43 44 45 46 DD46 FD46 06 e E g C 4F 48 49 4A 4B 4C 4D 4E DD4E FD4E OE i s s D 57 50 51 52 53 54 55 56 DD56 FD56 16 t T e E SF 58 59 SA 5B 5C 5D 5E DD5E FD5E IE T H 67 60 61 62 63 64 65 66 006(, OF66 26 N L 6F 68 69 6A 6B 6e 6D 6E OD61: F06E 2E R A ,- (HL) 77 70 71 72 73 74 75 g. 36 T (BC) 02 I n (DE) 12 o d. N I DD DD DD DD DD DD DD DD n X 77 70 71 72 73 74 75 36 d e y FD FD FD FD FD FD FD FD x 77 70 71 72 73 74 75 36 The register instructions have the format LD Rd, Rs where Rd and Rs are the destination and source register respectively. Register Indirect addresses are speci­ fied as (IX + d) or (IY + d). The displacement d is held in the third byte. Two instructions allow the accumulator to be loaded from or stored in a 16-bit address nn held in the second and third bytes: 142 Appendix 2: Z80 Instruction Set 143 LD A,nn - 3A nn and LD nn, A - 32 nn To move the contents of the I and R registers to and from the Accumulator there are four instructions: LDA,I - ED57 LD I,A - ED47 LDA,R - ED5F LDR,A - ED4F 16-bit Load Operations Re gister -register LD SP,HL - F9 LD SP,IX -DDF9 LD SP,IY -FDF9 Immediate operand LD BC,nn - 01 nn LDDE,nn - 11 nn LD HL, nn - 21 nn LD SP, nn - 31 nn LDIX,nn - DD 21 nn LD IY, nn - FD 21 nn Absolute address LDBC,(nn) -ED48nn LDDE,(nn) -ED58nn LD HL, (nn) - 2A nn LD SP, (nn) - ED 7B nn LD IX, (nn) - DD2Ann LD IY, (nn) - FD 2A nn LD (nn), BC - ED 43 nn LD (nn), DE - ED 53 nn LD (nn), HL - 22 nn LD (nn), SP - ED 73 nn LD (nn), IX - DD22 nn LD (nn), IY - FD 22 nn Stack operations PUSH AF - F5 PUSH BC - C5 PUSH DE - D5 PUSH HL - E5 PUSH IX - DD E5 PUSH IY - FD E5 POP AF - 01 POPBC -Cl POPDE -01 POPHL -El POPIX -DDEI POPIY - FDEI Exchanges EX AF ,AF' - 08 EXX' - D9 EX DE,HL - EB EX (SP),HL - E3 EX (SP),1X - DD E3 EX (SP),IY - FD E3 Block Transfers Load and Increment - LDI - ED AO - LD (DE), (HL), INC HL and DE, DEC BC. Load, Increment and Repeat - LDIR - ED BO - Repeated execution of LDI until BC = O. Load and Decrement - LDD - ED A8 - LD (DE), (HL),DEC HL and DE,DEC BC. Load, Decrement and Repeat - LDDR - ED B8 - Repeated execution of LDD until BC = O. Register HL holds source address. Register DE holds destination address; Register BC is Byte Counter. 144 An Introduction to Low Level Programming for Microprocessors Block Searches Four block search instructions operate in a similar manner to the above block transfers. Each item is compared with the contents of the accumulator and the zero flag is set when a match is found. In the repeated operation the search ends when either a match is found or the byte count in register BC falls to zero. Compare and Increment - CPI - ED Al Compare, Increment and Repeat - CPIR - ED Bl Compare and Decrement - CPD - ED A9 Compare, Decrement and Repeat - CPDR - ED B9 Accumulator, Flag, and CPU Operations Decimal Adjust Acc. DAA 27 Complement Acc. CPL 2F Negate Acc. (2's Comp.) NEG ED 44 Complement Carry Flag CCF 3F Set Carry Flag SCF 37 No Operation NOP 00 Halt HALT 76 Disable Interrupts DI F3 Enable Interrupts EI FB Set Int. Mode 0 IMO ED 46 Set Int. Mode 1 IMI ED56 Set Int. Mode 2 1M2 ED 5E Restart Group Vector Address 0000 0008 0010 0018 0020 0028 0030 0038 Instruction RST 0 RST 1 RST 2 RST 3 RST 4 RST 5 RST 6 RST 7 Op. Code C7 CF D7 DF E7 EF F7 FF Appendix 2: Z80 Instruction Set 145 8-bit Arithmetic and Logic Operations SOURCE Register Addressing Reg. Indexed Imm. Ind. A B C D E H L (HL) IX IY ADD 87 80 81 82 83 84 95 86 DO FD C6 86 86 AOC 8F 88 89 8A 8B 8C 80 8E OD FD CE 8E 8E SUB 97 90 91 92 93 94 95 96 OD FD D6 96 96 SBC 9F 98 99 9A 9B 9C 9D 9E DD FD DE 9E 9E AND A7 AO Al A2 A3 A4 AS A6 DD FD E6 A6 A6 XOR AF A8 A9 AA AB AC AD AE DO FD EE AE AE OR B7 BO Bl B2 B3 B4 B5 B6 OD FD F6 B6 B6 CP BF B8 B9 BA BB BC BD BE DD FD FE Compare BE BE INC 3C 04 OC 14 lC 24 2C 34 OD FD - Increment 34 34 DEC 3D 05 OD 15 lD 25 2D 35 OD FD - Decrement 35 35 The third byte of the indexed instructions carries the displacement.