TABLE OF CONTENTS Page 3 - Hard-Wired Forth: Harris's RTX-2000 (Embedded Systems Programming, February 1989). Page 13 -A New Breed of Microcontroller (Embedded Systems Programming, March 1989). Page 15 - Three RTX Development Systems (Embedded Systems Programming, August 1989). mHARRIS Page 2 BY ERNEST L. MEYER Reprinted from Embedded Systems Programming, · February 1989. Miller Freeman Publications. All rights reserved. - is fashionable these days, but for some real-time tasks Forth could be a better choice. In fact, ru­ mor has it that a number ofC programmers actually write C code during the day and then rewrite the functions in Forth at night. The manag­ ers think the code is in C, but the pro­ grammers can get the application work­ ing much more easily using Forth. With the advent of Forth-based mi­ crocontrollers, programmers no longer need to delude management in such a devious manner. The R TX microcon­ troller family, now available in produc­ tion quantities from Harris Semicon­ ductor, uses a subset of Forth instruc­ tions as op codes. Because there's no intermediate assembly language be­ tween the high-level constructs and the final machine code, the Forth instruc­ tions written by the programmer have direct and predictable machine-code equivalences. Not only does this simplify the con­ struction of efficient real-time routines, but once it's decided that the R TX real­ ly is the best choice for an application, the programmer is free to write the ap­ plication code in Forth. The processor itself can be custom­ ized in hardware for a wide range of specific application requirements. Ad­ ditional ALUs, multipliers, registers, and stacks can be added right inside the microcontroller's main data paths. Alternatively, on-chip stacks could be extended or a cache or UART added; D/ A and A/D interfaces could even be added on-chip, although the analog cir­ cuitry would make the chip somewhat more difficult to manufacture. EMBEDDED SYSTEMS PROG.RAMMING • FEBRUARY 1989 Page 3 • Harris Semiconductor's family of RTX microcontrollars uses a subset of Forth instructions as op codas. There's no intermediate assembly language, so Forth instructions written by the programmer have direct and predictable machine-coda equivalences. Page 4 EMBEDDED SYSTEMS PROGRAMMING • FEBRUARY 1989 Hard-Wired Forth FORTH-BASED HARDWARE ARCHITECTURE n the abstract, a chip with a subset of Forth instructions as op codes I has a number of advantages for real-time embedded applications. For example, think of the benefits Forth of­ fers for real-time tasks. It's fully reen­ trant. Direct control of the data and in­ struction stacks allows more intimate contact with branches, conditional loops, and interrupt functions than oth­ er languages usually offer. And reverse Polish notation, because it more closely represents the actual activity of the pro­ cessor, allows the designer to think more Higher-speed microcontrollers are also The RTX offers clearly about what's happening than do available at a debatably lower cost. And the "easier" code- and data-ordering Forth compilers can be used for the several advantages mechanisms used by other high-level more generic microprocessor hardware. languages. Even if the compiled Forth code uses over generic On the other hand, no chip will ever twice as many clock cycles on a generic reach the ideal, however close it man­ 25-MHz microcontroller as would the microcontrollers­ ages to approach it. A chip that uses same application on the 10-MHz RTX Forth instructions as op codes is bound microcontroller, the final system still predictabil ity, code to have some drawbacks. Most obvious­ works faster with a generic processor ly, it's not the ideal choice for other high­ running at a significantly higher clock language uniformity, level languages. With a more generic speed. architecture, it's certainly possible to The R TX microcontroller does offer lower system use different high-level languages for four advantages over generic microcon­ different applications and still use the trollers-predictability, code language speed, and potential same chip. Although cross-compilers uniformity, lower system speed, and po­ will no doubt become available for the tential customization-that can offset customization­ Forth chip at some stage, the chip is un­ the disadvantages. likely to offer the same level of perfor­ First, because high-level instructions that can off set mance with other high-level languages with direct machine-code correspon­ as it does with Forth. dences are used, it's much easier for the the disadvantages code developer to determine how long a IRRESISTIBLE FEATURES task will take. This is particularly im­ of high cost and ta pragmatic level, the 16-bit portant in real-time applications, where R TX microprocessor is not operations must be completed within reduced A cheap, with a unit cost of $190 strict time slots. in 1,000-piece quantities and a price tag Second, the developer can use the performance when of $3,000 for the complete development same language for critical functions as system (not including the host com­ for the rest of the code. Since applica­ used with other high­ puter). And the clock speed, at. 10 tions tend to use 10% of the code 90% of MHz, is comparatively low. the time, the critical sections are usual­ level languages. Other manufacturers offer 16-bit ly hand-coded in assembler. If the ma­ microcontrollers with similar clock chine code is simply a subset of the high­ speeds at a substantially lower cost. level code, however, there's no need to EMBEDDED SYSTEMS PROGRAMMING • FEBRUARY 1989 Page 5 link routines in different languages. Writing all the code in Forth also sim- plifies debugging. Unfortunately, these advantages mean very little to hardware designers. Luckily, two other benefits offered by IUH Register :a the RTX methodology should sway Q ~ lilJLR Register them. First, the use ofa 10-MHz rather ~ than 25-MHz microcontroller results in ~"' NEXT Register lower system speed, so the other chips in c: i 255-Word- the system don't need to run at ultra- Deep Stack Stack Pointer high speeds. And since cache memories aren't necessary at 10 MHz, system cost is lower. Lower-speed components also sim- plify board design. Even CMOS be- Scratchpad Register comes difficult to handle at speeds over 20 MHz, when transmission line effects can ~ause erroneous device triggering and corners in the wire traces can cause signal reflections. The hardware de- signer will therefore prefer a lower- speed processor from the standpoints of ~ Interrupt Vector ~ ~ board design effort and overall system Interrupt Base cost, ev.en if the processor itself is more Data Page Register expensive. Code Page Register A second advantage for hardware designers is that the structure of the User Page Register RTX chip permits them to customize User Page Register hardware for particular requirements Index Base Re ister by adding functional units to the micro- controller core. The functions can then Instruction Register be accessed directly by the software as an integral part of the microcontroller. Index Register ... II! Figure 1 is a high-level diagram of .s =~ 255-Word i§~ the chip core. The user can hang addi- Return Stack Stack Pointer ... ~ tional functional units on the ASIC bus U ~I 'P -t;~ (visible on the right side of the figure). If ~ !tJ ... i speed isn't a critical issue, functional ~ ...."' units can be hung on the ASIC bus off- Q"' L.J ...Cl> Figure 1 High-level diagram of RTX microcontroller core. Page 6 EMBEDDED SYSTEMS PROGRAMMING • FEBRUARY 1989 If speed is a Data is always shifted on- and off­ chip through the NEXT register. Not paramount issue and shown in the figure is the SWAP unit, which can swap the first and second Hard-Wired cost is not a severe bytes in the NEXT register at any time without cycle overhead. As a result, the limitation, resources chip can be used with both "big endian" Forth and "little endian" memory architec­ can be placed on­ tures, permitting compatibility with both Motorola- and Intel-like memory­ chip. Up to eight devices can be directly chip. Although this addressing schemes. addressed on the ASIC bus via address Multiplies and divides can be per­ lines AO-A2. A full bidirectional 16-bit raises chip cost formed by loading the two multipli­ data bus is then available between the cands sequentially into the multiplier additional functional units on the ASIC substantially, the unit from the NEXT register. The least sig­ bus and the microcontroller core. nificant byte of the 32-bit result is read­ If speed is a paramount issue and added peripheral able from the MULH register in the next cost isn't a severe limitation, the addi­ clock cycle. The upper eight bits of the tional resources can be placed on-chip. functionality works result can then be read in the subse­ Although this raises chip cost substan­ quent clock cycle by pushing the con­ tially, the added peripheral function­ about an order of tents of MULR into TOP. (The old contents ality works about an order of magnitude of TOP, the eight MSBs of the result, are faster. System cost may also be lower magnitude faster. automatically pushed into NEXT.) Two due to the higher degree of functional scratchpad registers are available for integration, which decreases the neces­ System cost may also storing intermediate values in divide sary PCB real estate for the system and and negative-exponent calculations. increases system reliability. be lower due to the The chip also contains three counters Of course, a similar hardware cus­ that can function in various modes. The tomization approach is available from higher degree of counters can be read independently into other vendors.