Writing Testbenches using SystemVerilog ____________________________ Writing Testbenches using SystemVerilog by Janick Bergeron Synopsys, Inc. 1 3 Janick Bergeron Verificationguild.com Writing Testbenches Using SystemVerilog Library of Congress Control Number: 2005938214 ISBN-10: 0-387-29221-7 ISBN-10: 0-387-31275-7 (e-book) ISBN-13: 9780387292212 ISBN-13: 9780387312750 (e-book) Printed on acid-free paper. ¤ 2006 Springer Science+Business Media, Inc. All rights reserved. This work may not be translated or copied in whole or in part without the written permission of the publisher (Springer Science+Business Media, Inc., 233 Spring Street, New York, NY 10013, USA), except for brief excerpts in connection with reviews or scholarly analysis. Use in connection with any form of information storage and retrieval, electronic adaptation, computer software, or by similar or dissimilar methodology now known or hereafter developed is forbidden. The use in this publication of trade names, trademarks, service marks and similar terms, even if they are not identified as such, is not to be taken as an expression of opinion as to whether or not they are subject to proprietary rights. Printed in the United States of America. 9 8 7 6 5 4 3 2 1 springer.com TABLE OF CONTENTS About the Cover xiii Preface xv Why This Book Is Important . xvi What This Book Is About . xvi What Prior Knowledge You Should Have . xviii Reading Paths . xviii Why SystemVerilog? . xix VHDL and Verilog . .xix Hardware Verification Languages . xx Code Examples . xxi For More Information . xxii Acknowledgements . xxii CHAPTER 1 What is Verification? 1 What is a Testbench? . 1 The Importance of Verification . 2 Reconvergence Model . 4 The Human Factor . 5 Automation . 6 Poka-Yoke . 6 Writing Testbenches using SystemVerilog v Table of Contents Redundancy . 7 What Is Being Verified? . 7 Equivalence Checking . 8 Property Checking . 9 Functional Verification . 10 Functional Verification Approaches . .11 Black-Box Verification . 11 White-Box Verification . 13 Grey-Box Verification . 14 Testing Versus Verification . 15 Scan-Based Testing . 16 Design for Verification . 17 Design and Verification Reuse . 18 Reuse Is About Trust . 18 Verification for Reuse . 19 Verification Reuse . 19 The Cost of Verification . 20 Summary . 22 CHAPTER 2 Verification Technologies 23 Linting . 24 The Limitations of Linting Technology . 25 Linting SystemVerilog Source Code . 27 Code Reviews . 29 Simulation . 29 Stimulus and Response . 30 Event-Driven Simulation . 31 Cycle-Based Simulation . 33 Co-Simulators . 35 Verification Intellectual Property . 38 Waveform Viewers . 39 Code Coverage . 41 Statement Coverage . 43 Path Coverage . 44 Expression Coverage . 45 FSM Coverage . 46 What Does 100 Percent Code Coverage Mean? . 48 Functional Coverage . 49 vi Writing Testbenches using SystemVerilog Coverage Points . 51 Cross Coverage . 53 Transition Coverage . 53 What Does 100 Percent Functional Coverage Mean? . 54 Verification Language Technologies . 55 Assertions . 57 Simulated Assertions . 58 Formal Assertion Proving . 59 Revision Control . 61 The Software Engineering Experience . 62 Configuration Management . 63 Working with Releases . 65 Issue Tracking . 66 What Is an Issue? . 67 The Grapevine System . 68 The Post-It System . 68 The Procedural System . 69 Computerized System . 69 Metrics . 71 Code-Related Metrics . 71 Quality-Related Metrics . 73 Interpreting Metrics . 74 Summary . 76 CHAPTER 3 The Verification Plan 77 The Role of the Verification Plan . 78 Specifying the Verification . 78 Defining First-Time Success . 79 Levels of Verification . 80 Unit-Level Verification . 81 Block and Core Verification . 82 ASIC and FPGA Verification . 84 System-Level Verification . 84 Board-Level Verification . 85 Verification Strategies . 86 Verifying the Response . 86 From Specification to Features . 87 Block-Level Features . 90 System-Level Features . 91 Writing Testbenches using SystemVerilog vii Table of Contents Error Types to Look For . 91 Prioritize . 92 Design for Verification . 93 Directed Testbenches Approach . 96 Group into Testcases . 96 From Testcases to Testbenches . 98 Verifying Testbenches . 99 Measuring Progress . 100 Coverage-Driven Random-Based Approach . 101 Measuring Progress . 101 From Features to Functional Coverage . 103 From Features to Testbench . 105 From Features to Generators . 107 Directed Testcases . 109 Summary . .111 CHAPTER 4 High-Level Modeling 113 High-Level versus RTL Thinking . .113 Contrasting the Approaches . 115 You Gotta Have Style! . .117 A Question of Discipline . 117 Optimize the Right Thing . 118 Good Comments Improve Maintainability . 121 Structure of High-Level Code . 122 Encapsulation Hides Implementation Details . 122 Encapsulating Useful Subprograms . 125 Encapsulating Bus-Functional Models . 127 Data Abstraction . 130 2-state Data Types . 131 Struct, Class . 131 Union . 134 Arrays . 139 Queues . 141 Associative Arrays . 143 Files . ..