INTERNATIONAL JOURNAL OF MATHEMATICS AND COMPUTERS IN SIMULATION VU Meter Driver Simulation and Design Martin Pospisilik, Milan Adamek • the reaction time of the VU meter should be short Abstract—This paper deals with a design, construction and enough so very short peaks could be displayed, practical testing of a VU meter driver that includes an accurate • it is convenient to take and display the logarithm of the rectifier and logarithmical driver of a pointer-type gauge. The logarithm is taken from the rectified signal by employing a measured value because of the typical character of the capacitor discharge voltage curve. Several software simulations audio signal. were made in order to proof the circuit design. Then a simple To meet these requirements, the advanced rectifier and rectifier and logarithmiser was designed and built in order these driver for analog VU meter was designed and built. When simulations were proved and afterwards, based on the gained designed, many simulations were processed with the aid of experience, the more complex design of the VU meter driver was created. The paper incorporates mathematical description of the Multisim software. The performance of the built circuit was circuit, simulation results and results gained when the simple physically tested and the results achieved were comparable to driver circuit underwent several physical tests as well as further the results of the simulations. Based on this experience a more propositions for practical extensions of the designed circuit. complex 2-channel VU meter driver was designed and built. Primarily, this circuit was designed to be used in a vacuum Keywords—Hardware logarithm processing, VU meter, audio valve amplifier as a power indicator. Therefore, several initial signal rectifier, gauge driver conditions may seem to be quite unusual, for example the power supply voltage of 6.3 V. However, the main principle I. INTRODUCTION can be applied to a wider variety of applications. NALOG audio signal levels are often expressed in A decibels compared to one reference level. Analogous VU II. LOGARITHMICAL PWM MODULATION meters are usually equipped with a non-linear decibel scale which stem from the definition of a ratio unit [dB]. In this case The basic aim was to employ a quite simple method of only a simple front end rectifier is sufficient for a satisfactory processing a pulse-width modulation by a comparator- level indication. However, it is more comfortable to take and connected operating amplifier. The voltage the logarithm is display directly the logarithm of the voltage level of the signal taken of is periodically compared to a reference voltage that because then we gain an advance of a linear gauge scale. In can be described by the following equation: addition, the gauge range is usually extended to at least 30 dB. −nTt − 0 There are several requirements that should be met by the τ REF 0 ⋅= 0 );,0; ∈〈∈ NnTteUu (1) accurate VU meter: Where: • Symmetrical processing of the AC signal voltage with low distortion observing the sufficient bandwidth, • U0 is the amplitude of the reference voltage [V], • accurate measuring of the peak value (in audio systems • t is time flowing throughout the period T0 [s], there is usually a need to display peak values to prevent the signal from clipping the peaks), • T0 is a period of pulse width modulation [s], • the peak value should be displayed for a period of time • n is the order of the appropriate period [-], that is long enough so the user could clearly see it on • τ is a time constant defining the voltage slope [s]. the scale, To get the best resolution we need to obtain the highest possible amplitude of the reference voltage. Ideally, uREF lies Manuscript received June 29, 2011: Revised version received XXXXXXX. This work was supported by by the European Regional in the range between U0 = Ucc at t = 0 and 0 at t = T0. Development Fund under the project CEBIA-Tech No. Practically, we will let the voltage to drop to 10 % of U0 which CZ.1.05/2.1.00/03.0089 and by the Internal Grant Agency at TBU in Zlin, can be well implemented physically. Considering this level project No. IGA/45/FAI/10/D. must be achieved in a period of T0, we can determine the Martin Pospisilik is with the Tomas Bata University in Zlin, Faculty of optimal value of τ: Applied Informatics, nám. T.G. Masaryka 5555, 760 01 Zlin, Czech Republic (corresponding author to provide phone: +420 57-603-5228; e-mail: T − 0 [email protected]). τ T0 Milan Adamek is is with the Tomas Bata University in Zlin, Faculty of 1.0 0 eUU τ −=⇒⋅=⋅ (2) Applied Informatics, nám. T.G. Masaryka 5555, 760 01 Zlin, Czech Republic )1.0ln( (e-mail: [email protected]). Issue 5, Volume 5, 2011 454 INTERNATIONAL JOURNAL OF MATHEMATICS AND COMPUTERS IN SIMULATION The behavior of the signal is described in Fig 1. with a curve 1 uIN called “Modulator reference voltage” as a result of computer R = − ⋅ ln (7) simulations applied to the circuit the design of which is ln 0.1 U 0 described in this paper. One can see that the slope of the voltage is exponential. Comparing this voltage to a direct From the equation (7) we can see the logarithmic dependence voltage of a random level at the input of the modulator, the of R on the input voltage uIN. Because the level of signal in output of the modulator can be described with the following [dB] is defined as Briggsian logarithm of the ratio between the equation: measured and the reference level and the modulator, as deduced above, makes the Napierian logarithm, we need to recalculate the output of the modulator so as to order the N proper scale was achieved. According to [1] we can use simple 0 ⇔uIN < u REF u = (3) approximation: OUT O U⇔ u ≥ u CC IN REF logx ≈ 0.434 294⋅ ln x (8) Where: The behavior of a PWM modulator with a reference voltage according to (1) can be seen in Fig. 1. There are two input • u is the output voltage of the ideal modulator [V], OUT voltages (modulator input voltage and modulator reference • uIN is the input voltage of the modulator [V], voltage) and the appropriate output of the modulator displayed. • U is the supply voltage of the ideal modulator [V], cc At the output of the modulator we get two-state signal with • uREF is the reference voltage of the modulator the ratio R. Throughout the period T0 this signal can be described by equation (1) [V]. expressed with the aid of the Heaviside step function: uOUT = UCC ⋅ H( t −(1 − R ) ⋅ T0 ) ; t ∈ 〈 0, T0 ) (9) Integrating this signal in time, we get direct voltage corresponding to R. We can express the mean value with the successive equation: 1 T0 U = u dt MEAN ∫ OUT T0 0 T 1 0 =U ⋅ H t −1 − R ⋅ T dt Fig. 1 Modulator signals (simulation results) ∫ CC (() 0 ) T0 0 Considering a period of pulse width modulation T [s] and a ()1−RT0 T0 0 1 (10) period of time when the output of the modulator is in a high = ⋅ 0 dt + U dt ∫ ∫ CC T0 state (uOUT = Ucc) tH [s], the ratio of the output signal of the 0 ()1−RT0 modulator R can be simply described as: 1 (1−RT ) 0 T0 = ⋅([][]0 ⋅t0 + UCC ⋅ t ()1−RT ) t T 0 R = H (4) 0 T0 1 = ⋅()TURTURU0 ⋅CC −()1 − ⋅0 ⋅CC = ⋅ CC In order to determine the value of R we must find such time t T0 throughout the period of T0 in which uIN = uREF, because at this point lies the threshold of the comparator. Provided we III. CIRCUIT DESCRIPTION consider invariable direct voltage at the input of the modulator, The circuit was built on a single-layer PCB. A high emphasis we can describe the dependence of R on uIN (using equations 1, 2, 3, 4) as: was placed on ease of the construction and low cost of the components. Before the description of the practical t− nT − 0 construction is provided, let us shortly see how the circuit can τ uIN = const. = uREF = U0 ⋅ e (5) be particularized into several logical blocks. T u t A. Logical blocks of the circuit t = −0 ⋅ ln IN ; R = (6) The circuit can be particularized into several blocks that can ln 0.1 U 0 T0 be seen in Fig. 2. At the input of the circuit, there is an input Issue 5, Volume 5, 2011 455 INTERNATIONAL JOURNAL OF MATHEMATICS AND COMPUTERS IN SIMULATION buffer that accommodates this circuit to preceding circuits in B. Detailed description terms of the voltage level and the impedance of the signal. As The schematics of the circuit can be seen in Fig. 3. There are there are two rectifiers employed in the circuit in order to three pin terminals in the circuit. These terminals are marked improve the symmetry of either positive or the negative half- SL1 to SL3. SL1 serves to connect the power supply of 6.3 V. wave of the signal, one of the rectifiers must be frontended The pointer-type gauge is connected to SL3 and at SL2 there is with an inverter. Outputs of both rectifiers are then the input of the driver. The aim was to make the circuit as summarized by an analog summer and a simple peak memory. simple as possible. This is the reason why only three These blocks are simply based on a larger capacitor. The transistors and two integrated circuits are employed in the differentiator derivates the voltage on the peak memory schematics.