Cadence AMS Simulator User Guide Cadence AMS Simulator User Guide Product Version 1.0 September 2000 2000 Cadence Design Systems, Inc. All rights reserved. Printed in the United States of America. Cadence Design Systems, Inc., 555 River Oaks Parkway, San Jose, CA 95134, USA Trademarks: Trademarks and service marks of Cadence Design Systems, Inc. (Cadence) contained in this document are attributed to Cadence with the appropriate symbol. For queries regarding Cadence’s trademarks, contact the corporate legal department at the address shown above or call 1-800-862-4522. All other trademarks are the property of their respective holders. Restricted Print Permission: This publication is protected by copyright and any unauthorized use of this publication may violate copyright, trademark, and other laws. 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September 2000 1 Product Version 1.0 Cadence AMS Simulator User Guide Contents Preface .......................................................................................................................... 11 Related Documents . 11 Typographic and Syntax Conventions . 12 1 Getting Started with the AMS Simulator . 14 Language Support . 15 Memory Requirements . 15 Setting Up Your Design Environment . 15 Running the Cadence AMS Simulator . 17 Running ncverilog with a Single Step . 21 Running the Simulator Using Multiple Steps . 22 Understanding the Simulator Library Databases . 23 Using a Configuration . 24 2 Running With the ncverilog Command. 26 Overview . 27 How ncverilog Works . 29 ncverilog Command Syntax and Options . 30 ncverilog Command Option Details . 32 3 Setting Up Your Environment. 35 Overview . 36 The Library.Cell:View Approach . 36 The cds.lib File . 37 The Work Library . 38 cds.lib Statements . 39 cds.lib Syntax Rules . 40 September 2000 2 Product Version 1.0 Cadence AMS Simulator User Guide Example cds.lib File . 42 Binding One Library to Multiple Directories . 42 Directory Binding Rules . 43 Debugging cds.lib Files . 43 The hdl.var File . 45 hdl.var Statements . 46 hdl.var Variables . 47 hdl.var Syntax Rules . 53 Example hdl.var File . 55 Debugging hdl.var Files . 55 The setup.loc File . 57 setup.loc Syntax Rules . 57 Directory Structure Example . 58 4 Instantiating Analog Masters . 62 Overview . 63 Using Spectre Built-In and Verilog-AMS Primitives . 63 Using Subcircuits and Models Written in SPICE or Spectre . 64 Creating an Analog Primitive Table . 64 IPassing the Location of the Analog Primitive Table to the Compiler and Elaborator . 65 Using Inline Subcircuits . 65 5 Importing Verilog-AMS Modules into VHDL Modules . 66 Overview . 67 Generating a Shell with ncshell . 67 Restrictions . 68 Steps to Follow . 68 Example . 69 September 2000 3 Product Version 1.0 Cadence AMS Simulator User Guide 6 Compiling . 72 Overview . 73 ncvlog Command Syntax . 74 ncvlog Command Options Details . 76 Example ncvlog Command Lines . 77 hdl.var Variables . 79 Conditionally Compiling Source Code . 80 Controlling the Compilation of Design Units into Library.Cell:View . 80 7 Elaborating . 82 Overview . 83 ncelab Command Syntax and Options . 84 ncelab Command Options Details . 90 Example ncelab Command Lines . 92 hdl.var Variables . 93 How Modules and UDPs Are Resolved During Elaboration . 94 Enabling Read, Write, or Connectivity Access to Digital Simulation Objects . 94 Selecting a Delay Mode . ..