International Journal of Reconfigurable Computing Current Trends on Reconfigurable Computing Guest Editors: Jürgen Becker, Michael Hübner, Roger Woods, Philip Leong, Robert Esser, and Lionel Torres Current Trends on Reconfigurable Computing International Journal of Reconfigurable Computing Current Trends on Reconfigurable Computing Guest Editors: Jurgen¨ Becker, Michael Hubner,¨ Roger Wood, Philip Leong, Rob Esser, and Lionel Torres Copyright © 2008 Hindawi Publishing Corporation. All rights reserved. This is a special issue published in volume 2008 of “International Journal of Reconfigurable Computing.” All articles are open access articles distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited. Editor-in-Chief Rene´ Cumplido, INAOE, Mexico Associate Editors Peter Athanas, USA Andres D. Garcia, Mexico Heitor Silverio Lopes, Brazil Jurgen¨ Becker, Germany Reiner Hartenstein, Germany Liam Marnane, Ireland Neil Bergmann, Australia Scott Hauck, USA Eduardo Marques, Brazil Koen Bertels, The Netherlands Masahiro Iida, Japan Fernando Pardo, Spain Christophe Bobda, Germany Volodymyr Kindratenko, USA Marco Platzner, Germany Paul Chow, Canada Paris Kitsos, Greece Viktor Prasanna, USA Katherine Compton, USA Miriam Leeser, USA Gustavo Sutter, Spain Claudia Feregrino, Mexico Guy Lemieux, Canada Lionel Torres, France Contents Current Trends on Reconfigurable Computing,Jurgen¨ Becker, Michael Hubner,¨ Roger Woods, Philip Leong, Robert Esser, and Lionel Torres Volume 2008, Article ID 918525, 1 page SystemC Transaction-Level Modeling of an MPSoC Platform Based on an Open Source ISS by Using Interprocess Communication, Sami Boukhechem and El-Bay Bourennane Volume 2008, Article ID 902653, 10 pages A Game-Theoretic Approach for Run-Time Distributed Optimization on MP-SoC, Diego Puschini, Fabien Clermidy, Pascal Benoit, Gilles Sassatelli, and Lionel Torres Volume 2008, Article ID 403086, 11 pages An Embedded Reconfigurable IP Core with Variable Grain Logic Cell Architecture, Motoki Amagasaki, Ryoichi Yamaguchi, Masahiro Koga, Masahiro Iida, and Toshinori Sueyoshi Volume 2008, Article ID 180216, 14 pages Architecture-Level Exploration of Alternative Interconnection Schemes Targeting 3D FPGAs: A Software-Supported Methodology, Kostas Siozios, Alexandros Bartzas, and Dimitrios Soudris Volume 2008, Article ID 764942, 18 pages Multiobjective Optimization for Reconfigurable Implementation of Medical Image Registration, Omkar Dandekar, William Plishker, Shuvra S. Bhattacharyya, and Raj Shekhar Volume 2008, Article ID 738174, 17 pages Dynamic Hardware Development, Stephen Craven and Peter Athanas Volume 2008, Article ID 901328, 10 pages On the Use of Magnetic RAMs in Field-Programmable Gate Arrays,Y.Guillemenet,L.Torres,G.Sassatelli, and N. Bruchon Volume 2008, Article ID 723950, 9 pages Hindawi Publishing Corporation International Journal of Reconfigurable Computing Volume 2008, Article ID 918525, 1 page doi:10.1155/2008/918525 Editorial Current Trends on Reconfigurable Computing Jurgen¨ Becker,1 Michael Hubner,¨ 1 Roger Woods,2 Philip Leong,3 Robert Esser,4 andLionelTorres5 1 Universitat¨ Karlsruhe (TH), 76131 Karlsruhe, Germany 2 Queens University Belfast, Belfast BT7 1NN, Northern Ireland 3 Chinese University Hong Kong, Hong Kong 4 Xilinx Inc., San Jose, CA 95124, USA 5 Le Laboratoire d’Informatique, de Robotique et de Micro´electronique de Montpellier (LIRMM), Universit´e Montpellier II/CNRS, 161 Rue Ada, 34392 Montpellier, France Correspondence should be addressed to Jurgen¨ Becker, [email protected] Received 15 December 2008; Accepted 15 December 2008 Copyright © 2008 Jurgen¨ Becker et al. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited. This special issue covers actual and future trends on reconfig- of field-induced magnetic switching and thermally assisted urable computing given by academic and industrial special- switching magnetic RAMs in FPGA design, highlighting ists from all over the world. In the issue, Boukhechem and reductions in both power consumption and configuration Bourennane address transaction-level modeling, a promising time at power up when compared to classical SRAM-based technique for increasingly complex embedded system. They FPGAs. The work by Steiner and Athanas describes the present a technique for modeling, validating, and verifying computing infrastructure that needs to be included in order an open embedded platform which allows faster and more to allow a system to change its operation without requiring efficient architecture exploration. Puschini et al. argue that outside intervention. Together, we hope that this special issue future systems will have distributed decision making capabil- will serve as an introduction to users who have newly joined ity, one of which will be to control the voltage scaling in the the community as well as provide specialists with recent device. They apply game theory to the run-time optimization results in this field of research. of the frequency of multiprocessor SoC platforms, resulting in a temperature reduction. The work by Amagasaki et al. Jurgen¨ Becker outlines an approach for varying the granularity of an FPGA Michael Hubner¨ logic cell when implementing arithmetic and random logic. Roger Woods The resulting cell gives improved logic depth and needs less Philip Leong reconfiguration data when compared to a Xilinx Virtex-4 Robert Esser device. Siozios et al. have presented tools for exploration Lionel Torres of alternative interconnection schemes for 3D FPGAs which provide partitioning, placement and routing, and power estimation. The work on medical image registration by Dandekar et al. outlines a novel multiobjective optimization strategy for exploring the tradeoff between FPGA resources and implementation accuracy. Craven and Athanas present work on a high-level development environment for reconfig- urable designs, that leverages an existing high-level synthesis tool to enable the design, simulation, and implementation of dynamically reconfigurable hardware based on a C specification. Guillemenet et al. looked at the integration Hindawi Publishing Corporation International Journal of Reconfigurable Computing Volume 2008, Article ID 902653, 10 pages doi:10.1155/2008/902653 Research Article SystemC Transaction-Level Modeling of an MPSoC Platform Based on an Open Source ISS by Using Interprocess Communication Sami Boukhechem and El-Bay Bourennane UMR CNRS 5158, University of Burgundy, 9 Avenue Alain Savary B.P: 47870, 21078 Dijon Cedex, France Correspondence should be addressed to Sami Boukhechem, [email protected] Received 29 February 2008; Revised 20 May 2008; Accepted 18 August 2008 Recommended by Michael Hubner Transaction-level modeling (TLM) is a promising technique to deal with the increasing complexity of modern embedded systems. This model allows a system designer to model a complete application, composed of hardware and software parts, at several levels of abstraction. For this purpose, we use systemC, which is proposed as a standardized modeling language. This paper presents a transaction-level modeling cosimulation methodology for modeling, validating, and verifying our embedded open architecture platform. The proposed platform is an open source multiprocessor system-on-chip (MPSoC) platform, integrated under the synthesis tool for adaptive and reconfigurable system-on-chip (STARSoC) environment. It relies on the integration between an open source instruction set simulators (ISSs), OR1Ksim platform, and the systemC simulation environment which contains other components (wishbone bus, memories, ..., etc.). The aim of this work is to provide designers with the possibility of faster and efficient architecture exploration at a higher level of abstractions, starting from an algorithmic description to implementation details. Copyright © 2008 S. Boukhechem and E.-B. Bourennane. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited. 1. Introduction at the earlier stages of the design flow before building a prototype, which is faster than HDL register-transfer level It has recently become possible to create complex embedded (RTL) simulation [2, 3]. systems called the multiprocessor system on chip (MPSoC), Traditionally, mixed language cosimulators are used [4] usually used for embedded applications. These systems for simulation which generates a communication overhead contain several microprocessors, memories (shared, private), between different simulators, often resulting in a significant shared busses, and peripherals integrated in a single die [1]. degradation in the execution time [5]. It is thus necessary to As a consequence, the system designer is confronted with use the same language for modeling software and hardware, new challenges and difficulties related to the integration and simulating these models at system level in a unified of such complex systems. So before any implementation, systems design approach. Many research and commercial it is necessary to validate by simulation the system to products provide cosimulation environments which com- be implemented. The chosen TLM simulation framework bine ISS, HDL simulators, or