Rochester Institute of Technology RIT Scholar Works Theses 12-2017 SystemVerilog Verification of Wishbone-Compliant Serial Peripheral Interface Avinash Srinivasan [email protected] Follow this and additional works at: https://scholarworks.rit.edu/theses Recommended Citation Srinivasan, Avinash, "SystemVerilog Verification of Wishbone-Compliant Serial eripherP al Interface" (2017). Thesis. Rochester Institute of Technology. Accessed from This Master's Project is brought to you for free and open access by RIT Scholar Works. It has been accepted for inclusion in Theses by an authorized administrator of RIT Scholar Works. For more information, please contact [email protected]. SystemVerilog Verification Of Wishbone-Compliant Serial Peripheral Interface by Avinash Srinivasan Graduate Paper Submitted in partial fulfillment of the requirements for the degree of Master of Science in Electrical Engineering Approved by: Mr. Mark A. Indovina, Lecturer Graduate Research Advisor, Department of Electrical and Microelectronic Engineering Dr. Sohail A. Dianat, Professor Department Head, Department of Electrical and Microelectronic Engineering Department of Electrical and Microelectronic Engineering Kate Gleason College of Engineering Rochester Institute of Technology Rochester, New York December, 2017 I dedicate my work to my mentor Professor Mark Indovina, my father Srinivasan Krishnarao, mother Ratna Srinivasan, brother Abhishek, sister-in-law Swathi and friends for their support during my thesis. Declaration I hereby declare that except where specific reference is made to the work of others, that all content of this Graduate Paper is original and have not been submitted in whole or in part for consideration for any other degree or qualification in this, or any other University. This research project is the result of my own work and includes nothing which is the outcome of work done in collaboration, except where specifically indicated in the text. Avinash Srinivasan December 19, 2017 Acknowledgements I wholeheartedly thank my graduate advisor and mentor Professor Mark Indovina for his continued support, feedback, encouragement and guidance through out my graduate career and research. I also thank Dr. Dorin Patru and Dr. Jayanthi Venkataraman for their support and guidance through out my graduate career. Abstract Synchronous serial interfaces provide economical on-board communication between the processor, digital to analog and analog to digital converters, memory, and other build- ing blocks on the chip. A number of Integrated Circuit (IC) manufacturers develop and produce components that are compatible with serial interfaces. The common serial inter- faces include Serial Peripheral Interface (SPI), Inter-Integrated Circuit (I2C), Universal Asynchronous Receiver Transmitter (UART), and Universal Serial Bus (USB). SPI is widely used and advantageous over other serial interfaces due to its features of simplicity, low cost, clock synchronous, and non-interrupting high-speed data transfer rate. SPI is the core controller of the design. An open source hardware computer bus Wishbone is selected as the host controller enabling parallel data exchange for faster communication. Both the hardware buses employ a master-slave configuration which makes the bus-interfacing easier. This research presents a verification environment using SystemVerilog for the SPI Mas- ter device. An existing design from Open Cores is re-used, described as per latest speci- fications in Verilog at the Register Transfer Level (RTL) and is in conformity with the design-reuse methodology. This paper provides an understanding of the verification, lay- ered test benches, Object-Oriented Technology (OOT), SystemVerilog, SPI features, SPI advantages, disadvantages, and applications, SPI data transmission and transfer formats, SPI registers, SPI sub-system and Wishbone-SPI architecture, and the test bench devel- opment methodology. The focus is to understand how OOT and SystemVerilog improve productivity and functional coverage in a verification environment by the use of different constructs, constrained-random techniques, coverage, and assertions. A test bench was developed to verify the SPI master core. Testbench components include a random trans- action generator, a Wishbone driver, an SPI master as the design under test, a receiver as the SPI slave, a monitor with tasks to monitor the host and the core, test cases, and a scoreboard to record metrics, assertions and store expected and actual data. Contents Contents v List of Figures ix List of Tablesx 1 Introduction1 1.1 Research Goals . .4 1.2 Contributions . .4 1.3 Organization . .4 2 Verification6 2.1 Overview . .6 2.1.1 Aspects . .7 2.1.1.1 Functional . .8 2.1.1.2 Timing . .8 2.1.1.3 Performance . .8 2.1.2 Methods . .8 2.1.2.1 Simulation-based . .9 2.1.2.2 Emulation-based . .9 2.1.2.3 Formal . .9 2.1.2.4 Semi-Formal . .9 2.1.2.5 Assertion-based . 10 2.1.2.6 Co-verification of Hardware and Software . 10 2.2 Verification Plan: A Layered Approach . 10 2.3 Benefits of a Layered Approach . 14 Contents vi 3 SystemVerilog 16 3.1 Object-Oriented Technology . 16 3.1.1 Overview . 16 3.1.1.1 Abstraction . 17 3.1.1.2 Encapsulation . 17 3.1.1.3 Inheritance . 17 3.1.1.4 Polymorphism . 17 3.1.2 Benefits . 17 3.2 SystemVerilog . 18 3.2.1 Overview . 18 3.2.2 Benefits . 18 4 Serial Peripheral and Wishbone Interface 20 4.1 Overview . 20 4.2 SPI Features . 21 4.2.1 Data Transfer and Addressing . 21 4.2.2 Synchronization . 22 4.2.3 Error Detection and Data Integrity . 22 4.2.4 Host-side interface . 22 4.2.5 Performance . 22 4.3 SPI Advantages, Disadvantages and Applications . 23 4.3.1 Advantages . 23 4.3.2 Disadvantages . 23 4.3.3 Applications . 23 4.4 SPI Interfaces . 24 4.4.1 Master Out Slave In (MOSI) . 25 4.4.2 Master In Slave Out (MISO) . 25 4.4.3 Slave Select (SS) . 25 4.4.4 Serial Clock (SCK) . 25 4.5 SPI Data Transfer Modes and Formats . 25 4.5.1 CPHA Equals Zero Transfer Format . 26 4.5.2 CPHA Equals One Transfer Format . 27 4.6 SPI Sub-System . 28 4.7 SPI Registers . 30 Contents vii 4.7.1 Data Direction Control Register . 30 4.7.2 Control Register . 31 4.7.3 Status Register . 32 4.8 Beginning and Ending SPI Transfers . 33 4.9 Wishbone Bus Interface . 33 4.10 System Architecture . 37 5 Testbench Methodology and Results 39 5.1 Testbench Methodology . 39 5.2 Testbench Components . 41 5.2.1 Interface . 41 5.2.2 Transaction . 41 5.2.3 Driver . 41 5.2.4 Monitor . 42 5.2.4.1 Wishbone Monitor . 42 5.2.4.2 SPI Monitor . 42 5.2.5 Scoreboard . 42 5.2.6 Environment . 42 5.2.7 Test Case . 43 5.2.8 Top-Level . 43 5.3 Testbench Results . 43 5.3.1 Design’s Area, Power and Module Hierarchy . 43 5.3.2 Code Methodology . 44 5.3.3 Wishbone and SPI Transaction Waveforms . 45 5.3.3.1 Wishbone Transactions to SPI devices . 45 5.3.3.2 SPI Master-Slave Communication . 46 6 Conclusion 48 6.1 Future Work . 48 References 50 I Source Code 54 I.1 Transactions . 54 I.2 Interface . 57 Contents viii I.3 Driver . 59 I.4 Scoreboard . 63 I.5 Monitor . 65 I.6 Environment . 69 I.7 Testcase . 70 I.8 Test . 71 I.9 Design Under Test . 72 I.9.1 Clock Generator . 72 I.9.2 Shift Register . 75 I.9.3 SPI Master . 92 I.9.4 SPI Slave . 103 List of Figures 2.1 Verification Strategies . .7 2.2 Signal and Command Layers . 11 2.3 Functional, Signal and Command Layers . 12 2.4 Scenario, Functional, Signal and Command Layers . 13 2.5 Complete Layered Testbench . 14 4.1 Processor-SPI Interaction . ..