UNIVERSITI TUNKU ABDUL RAHMAN Assembly Techniques and Packaging Dr. Lim Soo King 03/25/2013 Table of Contents Page Chapter 3 Assembly Techniques and Packaging ........................... 63 3.0 Introduction .............................................................................................. 63 3.1 Assembly Technologies ............................................................................ 63 3.2.1 Electrical requirements ..................................................................................... 68 3.2.2 Mechanical and Thermal properties ................................................................ 72 3.2.3 Cost ...................................................................................................................... 75 3.3 Packaging Level Integration ................................................................... 75 3.3.1 Interconnect Levels ............................................................................................ 76 3.3.1 Interconnect Level 1 - Die-to-Package-Substrate............................................ 77 3.3.2 Interconnect Level 2 - Package Substrate to Board ........................................ 79 3.3.3 Multi-Chip Modules - Die to Printed Wire Board .......................................... 81 3.4 Assembly Techniques and Processes ...................................................... 83 3.4.1 Wafer Preparation ............................................................................................. 84 3.4.2 Die Attach ........................................................................................................... 85 3.4.2.1 Eutectic Die Attach .......................................................................................................... 86 3.4.2.2 Epoxy Die Attach ............................................................................................................. 86 3.4.3 Wire Bonding ...................................................................................................... 87 3.4.4 Molding/Glass Seal ............................................................................................. 88 3.4.5 Post Mold Cure/Leak Check ............................................................................. 90 3.4.6 Solder Dip/Tin Plate ........................................................................................... 90 3.4.7 Trim/Form .......................................................................................................... 92 3.4.8 Inspection ............................................................................................................ 92 Exercises .......................................................................................................... 92 Bibliography ................................................................................................... 94 - ii - List of Figures Page Figure 3.1: Variety of Package types for both plastic and hermetic surface mount and through-hole mount .......................................................................................... 64 Figure 3.2: A hermetic package showing the integrated circuit is decoupled from external environment ..................................................................................................... 65 Figure 3.3: A plastic package showing the integrated circuit is not decoupled from external environment ....................................................................................... 65 Figure 3.4: A plastic package showing the integrated circuit is not decoupled from external environment ....................................................................................... 66 Figure 3.5: Rent’s constant for varies class of chip and system figure .............................. 67 Figure 3.6: Dielectric constant of common packaging materials ....................................... 69 Figure 3.7: Cross sectional structure for impedance control. (a) Micro-strip line, (b) Strip line, and (c) coplanar structure......................................................................... 70 Figure 3.8: Typical types of noise; (a) cross talk noise and (b) switching noise ............... 71 Figure 3.9: Cross sectional view of multi-layer lead frame package and the heat transfer mechanism ....................................................................................................... 74 Figure 3.10: Integrated circuit packaging level ................................................................... 76 Figure 3.11: Interconnect hierarchy in traditional integrated circuit packaging .................. 77 Figure 3.12: Wiring bonding connecting pad and lead ........................................................ 77 Figure 3.13: Typical conductance and inductance of package type and wire ...................... 78 Figure 3.14: Automated tap bonding (a) polymer with imprinted wire pattern and (b) die attach using solder bump ................................................................................. 78 Figure 3.15: Flip-chip bonding ............................................................................................... 79 Figure 3.16: Printed circuit board mounting approach. (a) through-hole mounting and (b) surface mounting .............................................................................................. 79 Figure 3.17: Commonly use package (1) leadless carrier, (2) DIP, (3) PGA, (4) small outline IC, (5) quad flat pack, and (6) PLCC ................................................... 80 Figure 3.18: Parameters of various chip carriers .................................................................. 81 Figure 3.19: Ball grid array packaging; (a) cross-section, (b) photo of PGA bottom .......... 81 Figure 3.20: An avionics processor module. Courtesy of Rockwell International .............. 82 Figure 3.21: Generic electronics packaging assembly sequence for plastic and ceramic package ............................................................................................................ 84 Figure 3.22: The basic structure of a silicon device die attach with a metal preform .......... 86 Figure 3.23: Structure of ceramic dual inline package (cerdip) showing the base, the lead frame and a lid with sealing glass .................................................................... 88 Figure 3.34: Schematics of a multi-pot transfer-mold system showing small mold compound tablets with each large enough to fill a few cavities containing plastic strips ..................................................................................................... 90 Figure 3.25: Molded plastic package strip showing short between tips of the lead, tight bar and guide pin hole ............................................................................................ 91 Figure 3.26: The formed molded plastic dip package strip shows that tight bar has not been removed............................................................................................................ 91 Chapter 3 Assembly Techniques and Packaging _____________________________________________ 3.0 Introduction Assembly techniques and packaging involve process of choosing the right type of package for a particular integrated circuit type and assemble the integrated circuit in the form of die into package that can be used for application. 3.1 Assembly Technologies There are many assembly technologies available in today’s assembly of integrated circuit into package device that can be used to insert into printed wire board PWB for application. The most common assembly technologies are the plastics and hermetic assembly technologies. The plastic assembly can be sub- divided into various package style both for surface mount SM and through-hole TH mount assembly techniques. Plastic package styles can be plastic dual inline package PDIP, plastic quad flat package PQFP, single outline package SOP, plastic leadless chip carrier PLCC, small outline integrated circuit SOIC etc. The technology to assemble these package various especially the wire bond, mold, and plating operation. The overview of the package types is shown in Fig. 3.1. Note that no all available package styles are shown. Hermetic assembly technology is basically used to assemble high reliability integrated circuit that are used in industrial, military, and outer space applications. In this case, the integrated circuit is decoupled from external environment by a vacuum-tight enclosure. Common packages that are assembled using this technology are ceramic dual inline package CDIP, pin grid array PGA, ball grid array BGA etc. An A typical hermetic package with a silicon chip placed in the cavity of a ceramic-based package and wedge-bonded to make electrical connections to the terminals on the package is shown in Fig. 3.2. - 63 - 03 Assembly Techniques and Packaging Figure 3.1: Variety of Package types for both plastic and hermetic surface mount and through-hole mount - 64 - 03 Assembly Techniques and Packaging Figure 3.2: A hermetic package showing the integrated circuit is decoupled from external environment Plastic assembly technology is usually used to assembly high volume, low cost integrated circuit. The integrated circuit or die is not decoupled from external environment. The die is in contact with epoxy resin, whereby in long run environment contaminant can penetrate the plastic to reach the integrated circuit causing reliability issue. However, with today’s technology, plastic package device begins gain acceptable for housing