DESIGN AND IMPLEMENTATION FOR A MULTI- STANDARD TURBO DECODER USING A RECONFIGURABLE ASIP By Eid Mohamed Abdel-Hamid Abdel-Azim A Thesis Submitted to the Faculty of Engineering at Cairo University in Partial Fulfillment of the Requirements for the Degree of MASTER OF SCIENCE in ELECTRONICS AND ELECTRICAL COMMUNICATIONS ENGINEERING FACULTY OF ENGINEERING, CAIRO UNIVERSITY GIZA, EGYPT 2013 DESIGN AND IMPLEMENTATION FOR A MULTI-STANDARD TURBO DECODER USING A RECONFIGURABLE ASIP By Eid Mohamed Abdel-Hamid Abdel-Azim A Thesis Submitted to the Faculty of Engineering at Cairo University in Partial Fulfillment of the Requirements for the Degree of MASTER OF SCIENCE in ELECTRONICS AND ELECTRICAL COMMUNICATIONS ENGINEERING Under the Supervision of Dr. Ahmed F. Shalash Dr. Hossam A. H. Fahmy ………………………………. ………………………………. Associate Professor, Associate Professor, ELECTRONICS AND ELECTRICAL ELECTRONICS AND ELECTRICAL COMMUNICATIONS Department COMMUNICATIONS Department Faculty of Engineering, Cairo University Faculty of Engineering, Cairo University FACULTY OF ENGINEERING, CAIRO UNIVERSITY GIZA, EGYPT 2013 DESIGN AND IMPLEMENTATION FOR A MULTI-STANDARD TURBO DECODER USING A RECONFIGURABLE ASIP By Eid Mohamed Abdel-Hamid Abdel-Azim A Thesis Submitted to the Faculty of Engineering at Cairo University in Partial Fulfillment of the Requirements for the Degree of MASTER OF SCIENCE in ELECTRONICS AND ELECTRICAL COMMUNICATIONS ENGINEERING Approved by the Examining Committee ____________________________ Dr. Emad Eldin Mahmoud Hegazi, External Examiner ____________________________ Prof. Dr. Mohamed M. Khairy, Internal Examiner ____________________________ Dr. Ahmed F. Shalash, Thesis Main Advisor ____________________________ Dr. Hossam A. H. Fahmy, Member FACULTY OF ENGINEERING, CAIRO UNIVERSITY GIZA, EGYPT May – 2013 Engineer’s Name: Eid Mohamed Abdel-Hamid Abdel-Azim Date of Birth: 26/8 /1986 Nationality: Egyptian E-mail: [email protected] Phone: 01280826660 Address: 139 Tahrir street, Dokki, Giza Registration Date: …./…./…….. Awarding Date: …./…./…….. Degree: Master of Science Department: Electronics And Electrical Communications Engineering Supervisors: Dr. Ahmed F. Shalash Dr. Hossam A. H. Fahmy Examiners: Dr. Emad Eldin Mahmoud Hegazi (External examiner) Prof. Dr. Mohamed M. Khairy (Internal examiner) Dr. Ahmed F. Shalash (Thesis main advisor) Dr. Hossam A. H. Fahmy (Member) Title of Thesis: Design And Implementation For A Multi-Standard Turbo Decoder Using A Reconfigurable ASIP Key Words: Turbo Decoder; ASIP; High-throughput; Parallel Architecture; Memory Conflict Summary: This thesis presents an efficient architecture to implement a turbo decoder using a scalable low energy application specific instruction-set processor (ASIP). The parallelism on the ASIP architecture is proposed to achieve the high-throughput demand for turbo decoder which is one of the most important requirements of the Fourth Generation (4G) wireless communication systems. We show the effects on the throughput, the area, and the hardware utilizations of the different turbo decoder schemes. Acknowledgments I would like to thank my supervisors, Dr. Ahmed F. Shalash and Dr. Hossam A. H. Fahmy, for their continuous support, advice, and guidance throughout my work. Special thanks to my dear mother, my dear father for their continuous support and encouragement during all working days. I also wish to express my appreciation to my colleagues at the Center of Wireless Studies (CWS). i Dedication To my mother, my father, my brothers and my sister. ii Contents Acknowledgmentsi Dedication ii Table of Contents iii List of Tables vi List of Figures vii List of Symbolsx List of Abbreviations xi Abstract xii 1 Introduction1 1.1 Introduction.................................1 1.2 Prior Work..................................2 1.2.1 Parallel Memory Access......................3 1.2.2 Unified and ASIP Turbo Decoder Works..............3 1.3 Design Flow.................................4 2 Turbo Codes6 2.1 Introduction.................................6 2.2 WiMAX convolution Turbo code......................6 2.2.1 Duo-binary Turbo Encoding....................6 2.2.2 WiMAX encoder..........................6 2.2.3 Internal interleaver.........................7 2.2.4 Circular state encoding.......................8 2.2.5 Rates and puncturing block.....................9 2.3 3GPP-LTE convolution Turbo code.....................9 2.3.1 Single binary Turbo Encoding...................9 2.3.2 LTE encoder............................ 10 2.3.3 Trellis termination......................... 10 2.3.4 Internal interleaver......................... 11 iii 3 Turbo Decoder Algorithms 12 3.1 SISO Decoding............................... 12 3.2 Log-MAP.................................. 13 3.3 Max-log-MAP................................ 14 3.3.1 Branch State Metric........................ 14 3.3.2 Forward State Metric....................... 14 3.3.3 Backward State Metric....................... 15 3.3.4 Extrinsic LLR........................... 16 3.4 Unified Radix-4 decoding algorithm.................... 17 3.5 Enhancement Max Log MAP........................ 18 3.6 Decoder Design Strategies......................... 18 3.7 Sliding Window Max-Log-MAP...................... 19 3.8 Parallel Sliding Window First Scheme................... 21 3.9 Parallel Sliding Window Second Scheme.................. 23 3.10 Trellis Termination............................. 23 4 Simulations of WiMAX and 3GPP-LTE Turbo Codes 24 4.1 Enhancement MAX Log MAP....................... 24 4.2 Effect of number of iterations........................ 24 4.3 Effect of Turbo interleaver block sizes................... 24 4.4 Effect of Turbo Modulation Schemes.................... 25 4.5 Effect of Symbol selection (Puncturing).................. 25 4.6 Effect of the Rayleigh selective fading channel on LTE.......... 25 4.7 Sliding Window MAX Log Map approximations............. 26 4.7.1 Parallel Sliding Window Effects Using Guard Window and bor- der states techniques........................ 26 4.8 Fixed point analysis............................. 27 5 Memory Conflict Analysis 37 5.1 Maximum Contention Free Interleavers.................. 37 5.2 Effect of Window Size on Memory Contentions.............. 38 5.3 The Second Scheme of Parallel Decoding Analysis............ 38 5.3.1 Decreasing the Number of Conflicts................ 38 5.3.2 Handling of the Conflicts...................... 41 5.3.3 Simulations Results for Memory Conflict............. 42 5.4 Memory Conflict Handling of The First Scheme.............. 43 6 ASIP Architecture 46 6.1 ASIP Architecture.............................. 46 6.2 State Metric Unit.............................. 46 6.2.1 First Configuration......................... 48 6.2.2 Second Configuration....................... 49 6.2.3 Third Configuration........................ 49 6.3 Memory Access............................... 53 6.4 Branch Metric Unit............................. 54 6.5 LLR Calculation Unit............................ 56 6.6 Instructions................................. 57 6.7 Interfacing Between SISOs......................... 58 iv 7 Inside The CPU 61 7.1 Micro-instructions.............................. 63 7.1.1 NOP Instruction.......................... 63 7.1.2 Call Instruction.......................... 64 7.1.3 Ret Instruction........................... 65 7.1.4 Goto Instruction.......................... 65 7.1.5 ZOL Instruction.......................... 66 7.1.6 LOOPNE Instruction....................... 67 7.1.7 ParSISO Instruction........................ 69 7.1.8 Initialize Instruction........................ 71 7.1.9 Mov Instruction........................... 72 7.1.10 StrData Instruction......................... 73 7.1.11 Decode Instruction......................... 73 7.1.12 Config Instruction......................... 74 8 Results and Future Works 75 8.1 Varying of the Window Sizes & the Parallel SISOs............ 75 8.2 Comparisons................................ 75 8.3 Future Works................................ 78 8.4 Conclusion................................. 80 Bibliography 81 v List of Tables 2.1 Wimax Turbo code permutation parameters................8 2.2 Circulation state lookup table (SC).....................8 2.3 LTE Turbo code internal interleaver parameters.............. 11 5.1 main parameters in different standards................... 43 5.2 Implementation parameters......................... 43 5.3 Comparison between two designs for data alignment block........ 44 5.4 Throughput comparison between two designs for LTE standard...... 44 5.5 Memory analysis for radix-2 implementations (all block sizes for each standard).................................. 44 5.6 Memory analysis for radix-4 implementations (all block sizes for each standard).................................. 44 5.7 Comparison of memory conflict for HSPA+ (Radix-4 scheme) with 2 par- allel SISOs................................. 44 6.1 Comparison of Three Configuration for one SISO............. 51 7.1 The op-code of the Instructions....................... 64 7.2 The NOP Instruction Description...................... 64 7.3 The Call Instruction description...................... 64 7.4 The Return Instruction description..................... 65 7.5 The Goto Instruction description...................... 66 7.6 The ZOL Instruction description...................... 68 7.7 The LOOPNE Instruction description................... 68 7.8 The ParSISO Instruction description.................... 69 7.9 The Initialize Instruction description.................... 72 7.10