Virtual Memory CSCI 2021: Machine Architecture and Organization Antonia Zhai Department Computer Science and Engineering University of Minnesota http://www.cs.umn.edu/~zhai With Slides from Bryant and O’Hallaron A System with Physical Memory Only Addresses generated by the CPU correspond directly to physical memory! Memory! 0:! Physical! 1:! Addresses! CPU! N-1:! Examples: most Cray machines, early PCs, nearly all embedded systems, etc. 4/8/15 CSCI 2021 2 1 Motivations for Virtual Memory Simplify Memory Management • Multiple processes resident in main memory • Each process with its own address space • Only “active” code and data is actually in memory • Allocate more memory to process as needed Use Physical DRAM as a Cache for the Disk • Address space of a process can exceed physical memory size • Sum of address spaces of multiple processes can exceed physical memory Provide Protection • One process can’t interfere with another. • because they operate in different address spaces. • User process cannot access privileged information • different sections of address spaces have different permissions 4/8/15 CSCI 2021 3 Motivation #1: Memory Management • Multiple processes can reside in physical memory. • How do we resolve address conflicts? • what if two processes access something at the same address? memory invisible to! kernel virtual memory! user code! %esp! stack! Memory mapped region ! Linux/x86 forshared libraries! process! memory ! runtime heap (via malloc)! image! uninitialized data (.bss)! initialized data (.data)! program text (.text)! forbidden! 0! 4/8/15 CSCI 2021 4 2 Motivation #2: DRAM a “Cache” for Disk • Full address space is quite large: • 32-bit addresses: ~4,000,000,000 (4 billion) bytes • 64-bit addresses: ~16,000,000,000,000,000,000 (16 quintillion) bytes • Disk storage is ~300X cheaper than DRAM storage • 80 GB of DRAM: ~ $33,000 • 80 GB of disk: ~ $110 • To access large amounts of data in a cost-effective manner, the bulk of the data must be stored on disk 80 GB: ~$110! 1GB: ~$200 ! DRAM! Disk! 4/8/15 CSCI 2021 5 Address Space • Address space • An ordered set of nonnegative integer addresses • Linear address space • Integers in the address space is consecutive • Virtual address space • The set of addresses generated by the CPU • {0, …, N-1} specified by n bits where 2n = N • Physical address space • Corresponds to the physical memory in the system • {0, …, M-1} specified by m bits where 2m = M 4/8/15 CSCI 2021 6 3 VM Address Translation Normally, M < N • Address Translation • MAP: V → P U {∅} • For virtual address a: • MAP(a) = a’ • if data at virtual address a at physical address a’ in P • MAP(a) = ∅ • if data at virtual address a not in physical memory • Either invalid or stored on disk 4/8/15 CSCI 2021 7 A System with Virtual Memory Examples: Memory! • workstations, servers, modern PCs, etc. 0:! Address Translation! 1:! Virtual! Physical! Addresses! 0:! Addresses! 1:! CPU! P-1:! M-1:! Disk! n Address Translation: Hardware converts virtual addresses to physical addresses via OS-managed lookup table (page table)! 4/8/15 CSCI 2021 8 4 Separate Virtual Address Spaces Virtual and physical address spaces divided into equal-sized blocks •! blocks are called “pages” (both virtual and physical) Each process has its own virtual address space •! operating system controls how virtual pages as assigned to physical memory 0! Virtual 0! Address Translation! Physical " Address VP 1! PP 2! Address " Space for VP... 2!! Space Process 1:" (DRAM)" N-1! (e.g., read/only PP 7! library code)! Virtual 0! Address VP 1! VP 2! PP 10! Space for ...! Process 2:" M-1! N-1! 4/8/15 CSCI 2021 9 VM Address Translation: Hit Processor! Hardware! Addr Trans! Main! a! Mechanism! Memory! a'! virtual address! part of the ! physical address! on-chip! memory mgmt unit (MMU)! 4/8/15 CSCI 2021 10 5 VM Address Translation: Miss page fault! fault! Processor! handler! Hardware! ∅! Main! Addr Trans! DISK! a! Mechanism! Memory! a'! OS performs! virtual address! part of the ! physical address! this transfer! on-chip! (only if miss)! memory mgmt unit (MMU)! 4/8/15 CSCI 2021 11 Page Faults What if an object is on disk rather than in memory? •! Page table entry indicates virtual address not in memory •! OS exception handler invoked to move data from disk into memory •! current process suspends, others can resume •! OS has full control over placement, etc. Before fault! After fault! Memory! Memory! Addr. Tran! Addr. Tran.! Virtual! Physical! Addresses! Addresses! Virtual! Physical! Addresses! Addresses! CPU! CPU! Disk! Disk! 4/8/15 CSCI 2021 12 6 Servicing a Page Fault (1) Initiate Block Read" •! Processor Signals Controller •! Read block of length P starting Processor" at disk address X and store Reg! (3) Read starting at memory address Y Done" •! Read Occurs •! Direct Memory Access (DMA) •! Under control of I/O controller Memory-I/O bus" •! I / O Controller Signals Completion (2) DMA •! Interrupt processor Transfer" I/O" •! OS resumes suspended process Memory" controller" diskDisk"" Diskdisk"" 4/8/15 CSCI 2021 13 VM Address Translation •! P = 2p = page size (bytes). •! N = 2n = Virtual address limit •! M = 2m = Physical address limit n–1" p" p–1" 0" virtual page number" page offset" virtual address! address translation" m–1" p" p–1" 0" physical page number" page offset" physical address! Page offset bits don’t change as a result of translation! 4/8/15 CSCI 2021 14 7 Page Tables Virtual Page! Memory resident! Number! page table! (physical page ! Valid! or disk address)! Physical Memory! 1! 1! 0! 1! 1! 1! 0! 1! 0! Disk Storage! 1! (swap file or! regular file system file)! 2 (n-p) entries 4/8/15 CSCI 2021 15 Address Translation via Page Table page table base register! virtual address! n–1! p! p–1! 0! VPN acts virtual page number (VPN)! page offset! as! table index! valid!access!physical page number (PPN)! if valid=0! then page! not in memory! m–1! p! p–1! 0! physical page number (PPN)! page offset! physical address! 4/8/15 CSCI 2021 16 8 Address Translation via Page Table 0x10000000! 0xdeadbeef! n–1! p! p–1! 0! VPN acts 0xdeadb! 0xeef! as! table index! valid!access!physical page number (PPN)! 0xabc if valid=0! then page! not in memory! m–1! p! p–1! 0! 0xabc! 0xeef! 0xabceef! 4/8/15 CSCI 2021 17 Address Translation via Page Table 0x10000000! 0x08042934! n–1! p! p–1! 0! VPN acts as! table index! valid!access!physical page number (PPN)! if valid=0! then page! not in memory! m–1! p! p–1! 0! 4/8/15 CSCI 2021 18 9 Page Table Operation Translation • Separate (set of) page table(s) per process • VPN forms index into page table (points to a page table entry) Computing Physical Address • Page Table Entry (PTE) provides information about page • if (valid bit = 1) then the page is in memory èUse physical page number (PPN) to construct address • if (valid bit = 0) then the page is on disk è Page fault 4/8/15 CSCI 2021 19 Protection Page table entry contains access rights information • hardware enforces this protection (trap into OS if violation occurs) Page Tables! Memory! Read?! Write?! Physical Addr! 0:! VP 0:! Yes! No! PP 9! 1:! Process i:! VP 1:! Yes! Yes! PP 4! VP 2:! No! No! XXXXXXX! • • • ! ! ! • • • ! ! ! • • • Read?! Write?! Physical Addr! VP 0:! Yes! Yes! PP 6! Process j:! VP 1:! Yes! No! PP 9! N-1:! VP 2:! No! No! XXXXXXX! • • • ! ! ! • • • ! ! ! 4/8/15 • • CSCI 2021• 20 10 Page Table Operation Checking Protection • Access rights field indicate allowable access • e.g., read-only, read-write, execute-only • typically support multiple protection modes (e.g., kernel vs. user) • Protection violation fault if user doesn’t have necessary permission page table base register virtual address nœ1 p pœ1 0 VPN acts virtual page number (VPN) page offset as table index valid access physical page number (PPN) if valid=0 then page not in memory mœ1 p pœ1 0 physical page number (PPN) page offset physical address 4/8/15 CSCI 2021 21 Multi-Level Page Tables Given: Level 2! Tables! • 4KB (212) page size • 32-bit address space • 4-byte PTE Problem: Level 1! Table! • Would need a 4 MB page table! è220 *4 bytes Common solution • multi-level page tables ...! • e.g., 2-level table (P6) • Level 1 table: 1024 entries, each of which points to a Level 2 page table. • Level 2 table: 1024 entries, each of which points to a page 4/8/15 CSCI 2021 22 11 An Example for 2 Level Page Table Page directory Up to 1024 • 1024 4-byte page directory entries page (PDEs) that point to page tables tables! • one page directory per process. 1024! • page directory must be in memory when PTEs! its process is running page directory! ...! • always pointed to by PDBR 1024! 1024! Page tables: PDEs! PTEs! • 1024 4-byte page table entries (PTEs) ...! that point to pages. 1024! • page tables can be paged in and out. PTEs! 4/8/15 CSCI 2021 23 Representation of Virtual Address Space P=1, M=1" •" Page 15! P=0, M=0" PT 3! •" Page 14! P=1, M=1" •" P=0, M=1" •" Page 13! Page Directory! Page 12! P=1, M=1" •" P=1, M=1" P=0, M=0" Page 11! •" PT 2! •" P=1, M=1" •" P=1, M=1" •" Page 10! P=0, M=0" P=0, M=1" •" •" Page 9! P=0, M=1" •" P=0, M=1" Page 8! PT 0! •" P=0, M=1" •" Page 7! P=0, M=0" •" P=0, M=0" •" Page 6! Simplified Example Page 5! Mem Addr! Page 4! • 16 page virtual address space Disk Addr! Page 3! In Mem! Flags Page 2! • P: Is entry in physical memory? Page 1! On Disk! Page 0! • M: Has this part of VA space been mapped? Unmapped! 4/8/15 CSCI 2021 24 12 Speeding up Translation with a TLB “Translation Lookaside Buffer” (TLB) •! Small hardware cache in MMU •! Maps virtual page numbers to physical page numbers •! Contains