WIRELESS CMOS FREQUENCY SYNTHESIZER DESIGN WIRELESS CMOS FREQUENCY SYNTHESIZER DESIGN by J. Craninckx Alcatel Mietec and M. Steyaert Katholieke Universiteit Leuven Springer-Science+Business Media, B.Y. A C.I.P. Catalogue record for this book is available from the Library of Congress. ISBN 978-1-4419-5034-5 ISBN 978-1-4757-2870-5 (eBook) DOI 10.1007/978-1-4757-2870-5 Printed on acid-free paper This printing is a digital duplication of the original edition. All Rights Reserved © I 998 Springer Science+Business Media Dordrecht Originally published by Kluwer Academic Publishers, Boston in 1998. Softcover reprint of the hardcover 1st edition 1998 No part of the material protected by this copyright notice may be reproduced or utilized in any form or by any means, electronic or mechanical' including photocopying, recording or by any information storage and retrieval system, without written permission from the copyright owner Second Printing 2001 Contents List of Figures ix List of Tables xv List of Symbols and Abbreviations xvii Preface xxv 1. INTRODUCTION 1 1.1 Modern Telecommunications 1 1.1.1 A Short History 2 1.1.2 Digital Cellular Systems 4 1.2 Integrating a Transceiver 6 1.3 Frequency Synthesizer Types 8 1.3.1 The Table-Look-Up Synthesizer 8 1.3.2 The Direct Synthesizer 9 1.3.3 The Phase-Locked Loop Synthesizer 10 1.3.4 Combination of Techniques 11 1.4 The Presented Work 12 2. PHASE-LOCKED LOOP FREQUENCY SYNTHESIZERS 15 2.1 Introduction 15 2.2 Definition of Phase Noise 16 2.3 PLL Fundamentals 20 2.3.1 Noise Characteristics 21 2.3.2 Transient Characteristics 23 2.3.2.1 Tracking 23 2.3.2.2 Acquisition 24 2.4 PLL Building Blocks 25 2.4.1 Phase Detector 25 2.4.1.1 Multipliers 26 2.4.1.2 Exclusive OR Gate 26 2.4.1.3 Flip-Flop 26 2.4.1.4 Phase-Frequency Detector 26 2.4.2 Loop Filter 30 2.4.2.1 First-Order PLL 30 2.4.2.2 Second-Order PLL 31 2.4.2.3 Third-Order PLL 32 v VI CMOS WIRELESS FREQUENCY SYNTHESIZER DESIGN 2.4.2.4 Charge-Pump PLL 34 2.4.3 Voltage-Controlled Oscillator 35 2.4.3.1 Crystal Oscillators 36 2.4.3.2 Relaxation Oscillators 38 2.4.3.3 Ring Oscillators 39 2.4.3.4 LC-Oscillators 40 2.4.3.5 OTA-C Oscillators 41 2.4.3.6 Other Configurations 41 2.4.4 Frequency Divider 41 2.4.4.1 Programmable Dividers or Counters 42 2.4.4.2 Prescalers 43 2.4.4.3 Fractional-N Synthesis 44 2.5 Conclusion 46 3. VOLTAGE-CONTROLLED OSCILLATOR PHASE NOISE 49 3.1 Introduction 49 3.2 Oscillator Theory 50 3.2.1 Q : the Quality factor 52 3.2.2 Active Inductors 53 3.2.2.1 Circuit implementation 53 3.2.2.2 Noise in Active Inductors 54 3.2.3 Passive Inductors 55 3.3 Phase Noise of a Basic Oscillator with Passive Inductor 57 3.3.1 Parallel Resistance Rp 57 3.3.2 Inductor Se ries Resistance R[ 59 3.3.3 Capacitor Series Resistance Re 60 3.3.4 Effective Resistance 61 3.3.5 Active Element GM 61 3.3.6 Conclusion 62 3.4 Phase Noise of a Basic Oscillator with Active Inductor 63 3.4.1 Inductor Current Noise Source 64 3.4.2 Inductor Voltage Noise Source 64 3.4.3 Total Noise 65 3.4.4 Conclusion 66 3.4.5 Comparison with Bandpass Filters 67 3.5 Phase Noise in Crystal Oscillators 68 3.5.1 Parallel Resistance Rp 68 3.5.2 Other Parasitic Resistors 70 3.5.3 Effective Resistance and Capacitance 71 3.5.4 Active Element GM 71 3.5.5 Noisy Inductor L" 72 3.5.6 Case Study : the CMOS Pierce Crystal Oscillator 73 3.5.7 Conclusion 75 3.6 Enhanced LC-Tanks 78 3.7 Other Phase Noise Sources 80 3.7.1 FM-modulation 81 3.7.2 1/1 Noise 83 3.8 State-of-the-Art Integrated VCOs 83 3.9 Conclusions 87 4. BONDING WIRE INDUCTANCE VCOS 89 4.1 Introduction 89 Contents vii 4.2 Bondin?r Wire Inductors 90 4.2.1 nductance Calculation 90 4.2.2 Bonding Wire Test VCO 93 4.2.3 Inductance Variation 95 4.2.4 Parasitics 98 4.2.4.1 Bonding Pad Parasitics 98 4.2.4.2 Inductor Series Resistance 103 4.2.4.3 Substrate Loss 104 4.2.4.4 Magnetic Coupling 106 4.3 Enhanced Bonding Wire LC-tank 106 4.4 Amplifier Design 111 4.4.1 Circuit Schematic 111 4.4.2 Bipolar or CMOS ? 112 4.4.3 Circuit Sizing 113 4.5 Measurement Results 114 4.6 Conclusions 118 5. PLANAR-INDUCTOR VCOS 121 5.1 Introduction 121 5.2 Planar Inductors 122 5.2.1 First-Order Inductance Calculation 125 5.2.2 Finite-Element Simulations 126 5.2.2.1 Metal Losses 128 5.2.2.2 Substrate Losses 132 5.2.2.3 Inductor Design Model 134 5.2.3 Hollow Coil Design Guidelines 135 5.3 Planar-LC VCO Design on a Heavily Doped Substrate 136 5.3.1 Coil Geometry 137 5.3.2 Amplifier Desi~ 139 5.3.3 Measurement esults 140 5.4 Planar-LC VCO Design on a Lowly Doped Substrate 142 5.4.1 Coil Geometry 144 5.4.2 Amplifier Design 149 5.4.3 Measurement Results 151 5.4.3.1 900-MHz Design 151 5.4.3.2 1.8-GHz Design 156 5.5 Conclusions 156 6. HIGH-FREQUENCY CMOS PRESCALERS 161 6.1 Introduction 161 6.2 Phase-Switching Dual-Modulus Prescaler Architecture 162 6.2.1 Conventional Topology 162 6.2.2 Phase-Switching TOPOIO~y 164 6.2.3 Variations on the Basic opology 166 6.3 A Dual-Modulus Divide-by-128/129 Prescaler in 0.7-f-/.,m CMOS 168 6.3.1 Circuit Desi~n 168 6.3.1.1 Fu I-Frequency Divide-by-2 168 6.3.1.2 Half-Frequency Divide-by-2 172 6.3.1.3 Phase-Selection 173 6.3.1.4 Low-Frequency Divide-by-32 176 6.3.2 Measurement Results 176 6.4 An Eight-Modulus Prescaler in O.4-f-/.,m CMOS 177 VllI CMDS WIRELESS FREQUENCY SYNTHESIZER DESIGN 6.4.1 Circuit Design 178 6.4.2 Measurements 181 6.5 Conclusions 183 7. A FULLY INTEGRATED CMOS PLL FREQUENCY SYNTHESIZER 187 7.1 Introduction 187 7.2 Phase-Frequency Detector 190 7.3 Loop Filter 190 7.3.1 Charge Pump 190 7.3.2 Filter Impedance 193 7.3.3 Active or Passive Filter? 195 7.4 Noise Aspects 197 7.4.1 Charge Pump Noise 197 7.4.2 Filter Impedance Noise 198 7.4.3 4-th Order PLL 199 7.5 Improved Loop filter 201 7.5.1 Filter topology 202 7.5.2 Transfer Functions 205 7.5.2.1 Open Loop Gain 206 7.5.2.2 Charge Pump Noise 207 7.5.2.3 Loop Filter Noise 208 7.5.3 Filter Optimization 208 7.6 Linearization 212 7.7 Measurements 217 7.7.1 Phase Noise Performance 220 7.7.2 Transient Characteristics 222 7.8 Conclusions 223 8. GENERAL CONCLUSIONS 227 Bibliography 233 Index 245 List of Figures 1.1 Components of a mobile telephone system 3 1.2· Architecture of the GSM system 4 1.3 Receiver architectures : (a) IF receiver; (b) Zero-IF receiver 7 1.4 Table-Iook-up frequency synthesizer 9 1.5 Direct synthesizer example 10 1.6 General block diagram of a phase-Iocked loop (PLL) frequency syn- thesizer 10 1.7 Direct digital frequency synthesizer 12 1.8 Dual-Ioop PLL frequency synthesizer 13 2.1 Phase noise in an oscillator output spectrum 17 2.2 Effect of oscillator phase noise in a receiver 18 2.3 Effeet of oseillator phase noise in a transmitter 18 2.4 Equivalenee between phase PSD and single-sided phase noise 19 2.5 PLL frequency synthesizer: (a) Block diagram; (b) State variable di- agram; (e) Feedback system 20 2.6 Phase noise transfer funetions in a PLL synthesizer: (a) VCO noise; (b) Referenee noise 23 2.7 (a) EXOR phase detector; (b) Operation; (c) Transfer charaeteristic 27 2.8 (a) Flip-flop phase deteetor; (b) Operation; (e) Transfer eharaeteristie 27 2.9 Harmonie frequeney contents of (a) EXOR PD; (b) Flip-flop PD 28 2.10 (a) Phase-frequeney deteetor; (b) Operation; (e) Transfer eharacteristic 29 2.11 Circuit implementation of a phase-frequeney deteetor without dead zone 30 2.12 Open loop gain Bode plot for a l-st order, type-l PLL 31 2.13 Open loop gain Bode plot for a 2-nd order, type-I PLL 32 2.14 Open loop gain Bode plot for a 3-rd order, type-l PLL 33 2.15 Loop filter implementation for a 3-rd order, type-2 PLL 33 2.16 Loop filter impedanee for a 3-rd order, type-2 charge-pump PLL 35 IX x CMOS WIRELESS FREQUENCY SYNTHESIZER DESIGN 2.17 An oscillator crystal : (a) Symbol; (b) Electrical model; (c) Impedance 36 2.18 Crystal oscillator circuits : (a) One-pin oscillator; (b) Pierce oscillator 37 2.19 Emitter-coupled multivibrator 38 2.20 Ring oscillator: (a) three-stage; (b) differential two-stage; (c) I-stage delay 39 2.21 Wien-bridge oscillator 41 2.22 (a) Asynchronous frequency divider; (b) Waveforms 42 2.23 (a) Synchronous frequency divider; (b) Waveforms 43 2.24 (a) Dual-modulus divide-by-4/5 prescaler; (b) Waveforms 44 2.25 Frequency divider with dual-modulus prescaler and pulse- and swallow- counters 45 2.26 PLL frequency synthesizer with fractional-N division 46 3.1 General feedback network 50 3.2 Basic LC-tuned osciIIator configuration 51 3.3 Active inductor : (a) Gyrator symbol; (b) Implementation; (c) Simu- lation of an inductor; (d) Equivalent noise sources 54 3.4 Equivalent circuit of a passive integrated inductor: (a) simple; (b) com- plete 56 3.5 Basic oscillator with noisy Rp 57 3.6 Basic oscillator with noisy R{ 59 3.7 Basic oscillator with noisy active inductor 64 3.8 Bandpass filter: (a) Circuit; (b) Bode plot 67 3.9 General model of a simulated crystal oscillator 69 3.10 Crystal oscillator with noisy Rp 69 3.11 Pierce crystal oscillator circuit schematic 73 3.12 Internal voltages in a crystal 76 3.13 (a) Low-voltage enhanced LC-tank with n in duc tors and n capacitors; (b) Internal voltages 79 3.14 Phase noise regions in an oscillator output spectrum 80 3.15 FM-modulation in a YCO 81 4.1 Pad-to-pad bonding wire example in a commercial IC [AD7886] 91 4.2 Differential bonding wire inductor 91 4.3 Physical structure of a bonding wire inductor for 2-D finite-element simulations 92 4.4 Finite-element simulation result for 2-D bonding wire inductor stucture 93 4.5 Bonding wire test VCO circuit diagram 94 4.6 Bonding wire test VCO microphotograph 94 4.7 Bonding wires of fixed length : (a) chip-to-chip; (b) chip-to-package- to-chip 95 4.8 SEM microphotograph