(IJACSA) International Journal of Advanced Computer Science and Applications, Vol. 4, No. 9, 2013 A Soft Processor MicroBlaze-Based Embedded System for Cardiac Monitoring El Hassan El Mimouni Mohammed Karim University Sidi Mohammed Ben Abdellah University Sidi Mohammed Ben Abdellah Fès, Morocco Fès, Morocco Abstract—this paper aims to contribute to the efforts of recent years, and has become also an important way to assert design community to demonstrate the effectiveness of the state of the heart’s condition [5 - 9]. the art Field Programmable Gate Array (FPGA), in the embedded systems development, taking a case study in the II. SYSTEM OVERVIEW biomedical field. With this design approach, we have developed a We have designed and implemented a prototype of basic System on Chip (SoC) for cardiac monitoring based on the soft embedded system for cardiac monitoring, whose functional processor MicroBlaze and the Xilkernel Real Time Operating block diagram is shown in the figure 2; it exhibits a modular System (RTOS), both from Xilinx. The system permits the structure that facilitates the development and debugging. Thus, acquisition and the digitizing of the Electrocardiogram (ECG) analog signal, displaying heart rate on seven segments module it includes 2 main modules: and ECG on Video Graphics Adapter (VGA) screen, tracing the An analog module intended for acquiring and heart rate variability (HRV) tachogram, and communication conditioning of the analog ECG signal to make it with a Personal Computer (PC) via the serial port. We have used appropriate for use by the second digital module ; the MIT_BIH Database records to test and evaluate our implementation performance. In terms of the resources A soft processor-based module digitizes and processes utilization, the implementation occupies around 70% of the used the ECG signal. FPGA, namely the Xilinx Spartan 6 XC6SLX16. The accuracy of the QRS detection exceeds 96%. A secondary module acts as a way to facilitate testing system with the standard ECG records contained in the Keywords—ECG; FPGA; Heart Rate Variability; MicroBlaze; standard MIT-BIH database [10]. QRS detection; SoC; Xilkernel This implementation is to be considered as a strong I. INTRODUCTION improvement and a migrating to advanced new technology, mentioned above, of one of our previous works [11]; it can also A Field Programmable Gate Array (FPGA) is a high be seen as a contribution to developing a more efficient and density Programmable Logic Device (PLD) that allows high low-cost biomedical instrumentation. performance data processing. Its digital signal processing (DSP) performance is derived from the ability to construct ECG signal is the measure, via electrodes acquiring the naturally parallel structures or modules, achieving a hardware voltage (potential difference) on the body surface, generated by multitasking. This rapid increase of complexity emerged also the heart's electrical activity. As illustrated by the figure 1, the the new concept of SoC that integrates most of the functions of ECG is characterized mainly by 5 waves reflecting the activity the end product into a single chip; this is encouraged by the of the heart during a cardiac cycle (R-R interval); these waves reuse of optimized Intellectual Properties (IPs), particularly soft are called P, Q, R, S and T; the Q, R, and S waves are treated and hard processors; in fact, FPGAs are nowadays so dense as a single composite wave known as the QRS complex. The that it is possible to embed a processor (soft or hard) on the ECG signal is typically characterized by maximum amplitude single chip and there is still enough room for eventual of 1 mV and a bandwidth of 0.05 Hz to 100 Hz [9, 12]. additional functionalities. Moreover, these FPGAs come with sophisticated software tools for the processor, like C/C++ compilers and a RTOS kernel; this improves the design abstraction and consequently the productivity [1 - 4]. The electrocardiogram signal (ECG) is one of the most commonly used in medical practice thanks to its non-invasive nature, simple acquisition process and the meaningful information it contains; the analysis of such information permits to evaluate the state of the heart. Thus, the cardiac monitoring by means the ECG is a standard practice in intensive care, emergency rooms, ambulatory monitoring, etc. It is worth noting that the cardiac rhythm monitoring by means Fig. 1. Typical ECG of a healthy person. the heart rate variability (HRV), increasingly studied in the 48 | P a g e www.ijacsa.thesai.org (IJACSA) International Journal of Advanced Computer Science and Applications, Vol. 4, No. 9, 2013 VGA Analog module Real ECG signal Instrum. Digital module Filtering Lead II Ampli. Analog To UART MicroBlaze-based Digital System Converter LPT - PC + ECG signal from MIT-BIH Gain Offset Database Digital To Analog Converter Fig. 2. System functional diagram block. III. ANALOG MODULE The Software Development Kit (SDK) that is an integrated development environment, complementary to We used the Lead II that is the most commonly used lead XPS used for C/C++ embedded software application for ECG ambulatory monitoring, because it’s a relative high- creation and verification. voltage deflection resulting in P, R and T waves. The reference electrode is connected to the right leg via an amplifier to reduce As development board, we have used the Nexys 3 of common mode noise, a principle commonly termed by Digilent that features Xilinx's Spartan-6 XC6SLX16 FPGA, “Right Leg Drive”. The two other electrodes, representing Lead 48 Mbytes of external memory, and enough I/O devices and II, attack an instrumentation amplifier (IA) we have achieved ports to host a wide variety of digital systems [16]. with off the shelf operational amplifiers, which present good performances, especially a relative good common mode A. Hardware rejection ratio (CMRR). The different types of noise are The foundation of the hardware of the design is created reduced by means analog filtering: low pass and anti-aliasing using the Base System Builder (BSB) wizard within XPS. This filter of 0-70 Hz, and notch filter for reducing noise effect of allows the use of pre-developed IPs cores with a series of 50 Hz of AC power line. Finally, the output signal gain and Buses and Interfaces to connect the various hardware elements offset of this stage are properly adapted to the analog to digital of the design. The figure 3 shows the architecture of our converter (ADC) of the digital module. implementation; the design consists of the main following IPs cores: IV. SOFT PROCESSOR-BASED DIGITAL MODULE MicroBlaze soft processor is the main and central Today’s FPGAs integrate existing IP cores achieving element of the entire architecture; in other words, it functionalities commonly used in the embedded systems world represents the central and processing unit (CPU) of the (GPIO, Timers, UART, SPI, VGA, etc.); they can be easily system. instantiated into a top-level design. Among them, the most important are the soft processors cores; indeed, the availability The Digital Clock Manager (DCM) primitive in FPGA of such embedded subsystems in FPGAs opens a whole new provides advanced clocking capabilities; it optionally world of possibilities. A soft or virtual processor is built by multiply or divide the incoming clock frequency to combining blocks of optimized HDL code inside an FPGA. In synthesize a new clock frequency. our case, it was the MicroBlaze, which is a reduced instruction Bus Local memory Bus (LMB) provides single-cycle set computer (RISC) optimized for implementation in Xilinx FPGAs [13]. access to on-chip RAM. The development of this module was guided by the On-chip dual-port block RAM (BRAM) stores Hardware/Software co-design techniques, which try to exploit processor’s program instructions and data; as the the synergy of Hardware and Software with the goal to application program exceeds the BRAM limit optimize and satisfy design constraints of a final product [14]. (32 Kbytes), the external SRAM is used for this Thus, as development tool, we have used the Xilinx Embedded purpose. Development Kit (EDK), which is a suite of tools and The Processor Local Bus (PLB) provides a connection Intellectual Property (IP) that permits the design of a complete to both on-and off-chip peripherals and memory. embedded processor system for implementation in a Xilinx FPGAs [15]. We mention in particular: Timer 0 is required by Xilkernel RTOS to tick its kernel. The Xilinx Platform Studio (XPS) that is the development environment used for designing the Timer 1 is used to generate an interrupt every 5 ms hardware aspect of an embedded processor system. (200 Hz) for ECG analog signal sampling, according to the Shannon theorem. 49 | P a g e www.ijacsa.thesai.org (IJACSA) International Journal of Advanced Computer Science and Applications, Vol. 4, No. 9, 2013 INTC Interruption Controller Timer 0 Xilkernel Timer Timer 1 ADC Timer GPIO 1 Switches ILMB GPIO 2 LEDs ILMB_CNTLR ILM INT R PLB BRAM B DLMB_CNTLR CLKCL ADC SPI DLMB K SPI 7 Segments SS Clock 50 MHz 100 MHz DCM UART/USB 25 MHz UART Converter PC TFT VGA Screen External EMC SRAM FPGA SPARTAN 6 XC6SLX16 Fig. 3. MicroBlaze-based hardware. General Purpose Input Output (GPIO) is used to SS is a customized IP from Digilent; it controls the communicate with simple human machine interface seven segments with time multiplexing, intended to (HMI) that consists of switches and LEDs. heart rate display; that is a good example for Hardware/Software co-design illustration; in fact, this INTC is an interrupt controller used to concentrate task could have been achieved by a certain C code multiple interrupt inputs from peripheral devices to a function executed by the CPU; this customized IP single interrupt output driving the unique processor offloads then the processor.