Europäisches Patentamt *EP000708405B1* (19) European Patent Office Office européen des brevets (11) EP 0 708 405 B1 (12) EUROPEAN PATENT SPECIFICATION (45) Date of publication and mention (51) Int Cl.7: G06F 13/40, G06F 1/32 of the grant of the patent: 24.05.2000 Bulletin 2000/21 (21) Application number: 95306666.9 (22) Date of filing: 21.09.1995 (54) Multiplexer and integrated processor incorporating same Multiplexer und integrierter Prozessor mit einem solchen Multiplexer Multiplexeur et processeur intégré pourvu d’un tel multiplexeur (84) Designated Contracting States: (74) Representative: Picker, Madeline Margaret et al AT BE DE DK ES FR GB GR IE IT LU NL PT SE Brookes & Martin, High Holborn House, (30) Priority: 19.10.1994 US 325906 52/54 High Holborn London WC1V 6SE (GB) (43) Date of publication of application: 24.04.1996 Bulletin 1996/17 (56) References cited: • PATENT ABSTRACTS OF JAPAN vol. 9 no. 163 (73) Proprietor: ADVANCED MICRO DEVICES INC. (P-371) ,9 July 1985 & JP-A-60 039237 (HITACHI) Sunnyvale, California 94088-3453 (US) 1 March 1985, • PATENT ABSTRACTS OF JAPAN vol. 14, no. 293 (72) Inventors: (P-1066) 25 June 1990 & JP-A-02 090 382 • Baum, Gary (HITACHI) 29 March 1990 Austin, Texas 78746 (US) • Quimby, Michael S. Austin, Texas 78748 (US) Note: Within nine months from the publication of the mention of the grant of the European patent, any person may give notice to the European Patent Office of opposition to the European patent granted. Notice of opposition shall be filed in a written reasoned statement. It shall not be deemed to have been filed until the opposition fee has been paid. (Art. 99(1) European Patent Convention). EP 0 708 405 B1 Printed by Jouve, 75001 PARIS (FR) EP 0 708 405 B1 Description [0001] This invention relates to a multiplexer. We will describe a device for multiplexing more than one set of signals to a single set of pins arranged on the output of an integrated processor. 5 [0002] Manufacturers have demonstrated an ability to place an increasing amount of circuitry upon a single monolithic semiconductor substrate or "chip". The advent of portable data processing systems, herein referred to as personal information devices ("PIDs"), has lead a push toward placing an even greater amount of circuitry on a single chip. As defined herein, PIDs include any portable CPU-based system, such as pocket personal computers (PCs), digital as- sistants (test units, meters, etc.), "smart" phones, and electronic calendars, organizers, booklets, etc. 10 [0003] Functional demands of modern PIDs typically require that they be data-intensive, view-intensive and/or voice- intensive. For example, a pocket personal computer may be called upon to perform extensive data calculations involving data-intensive functions. Additionally, a pocket personal computer may also require, for example, a detailed, objecto- riented display requiring view-intensive functions. On the other hand, a smart phone may require voice-intensive func- tions, and not necessarily view- and/or data-intensive functions. Therefore, an integrated processor system which is 15 intended for use within of a wide range of PID applications must include the necessary subsystems to accommodate all three types of functionality. [0004] In addition to the above technical features, an integrated processor for PIDs must also operate at low power within a small package outline, and should preferably be available at a low cost. Unfortunately, an effort to lower cost by reducing, for example, the pin-count of the integrated processor may require the elimination of certain desirable 20 subsystems of the integrated processor, thus limiting functionality and/or performance. Power consumption may sim- ilarly be adversely affected by the incorporation of certain subsystems or by the requirement of a variety of differing crystal oscillator circuits to clock the various subsystems. Integrated processors for PIDs which achieve acceptable performance capabilities while maintaining wide versatility, small size, low power consumption, and low cost are largely unavailable. 25 [0005] A high performance, versatile integrated processor is therefore desirable which is adaptable to data-intensive, view-intensive and/or voice-intensive PID applications. Such an integrated processor should additionally be charac- terized by small size, low power consumption, and low cost. [0006] JP-A-60 039237 discloses a known semiconductor integrated circuit device. The integrated circuit is provided with a microprocessor, a CRT control circuit and a multiplexer. An address signal from the microprocessor and an 30 address signal from the CRT circuit are fed to the multiplexer. The signals are switched in terms of time division by using a system clock from a pulse generating circuit. The address signal output by the multiplexer is provided to an external refresh memory. [0007] In accordance with a first aspect, the present invention provides a multiplexer apparatus for providing select output signals at the output of an integrated circuit as defined in accompanying claim 1. 35 [0008] In accordance with a second aspect, the present invention provides an integrated processor having the fea- tures recited in accompanying claim 5, which includes the multiplexer apparatus of the first aspect of the present invention. [0009] We will describe a highly integrated, low-power integrated processor. [0010] The integrated processor is fabricated on a single monolithic circuit and employs circuitry to accommodate 40 data-intensive, view-intensive and voice-intensive requirements of modern-day PIDs. Importantly, the integrated proc- essor includes a CPU core, a memory controller, and a variety of peripheral devices to achieve versatility and high performance functionality. The integrated processor consumes less power by provision of a clock control unit including a plurality of phase-locked loops for generating clock signals of differing frequencies to appropriately clock the various subsystems of the integrated processor. The clock signals provided to the various subsystems by the clock control unit 45 are derived from a single crystal oscillator input signal. Since only one external crystal oscillator circuit is required, power consumption is substantially reduced. A power management unit is further incorporated within the integrated processor to control the frequency and/or application of certain clock signals to the various subsystems, as well as to control other power management related functions. The pin-count of the integrated processor is finally minimized by allowing the selective multiplexing of certain external pins depending upon the desired functionality of the integrated 50 processor. In one user-defined mode, the external pins are allocated to an internal video controller, such as a CGA LCD controller. In another mode, the external pins are allocated to provide an external interface to selected lines of a CPU local bus of the integrated processor. In yet an additional mode, the external pins are allocated to provide an external interface to selected lines of a peripheral bus, such as an ISA-style bus, of the integrated processor. Wide versatility of the integrated processor is thereby advantageously achieved while minimizing the overall pin count of the 55 integrated processor. [0011] In one embodiment, the integrated processor system includes a CPU core and a memory controller connected to a CPU local bus. The integrated processor further includes a selected set of peripheral devices coupled to a peripheral interconnect bus including a bus interface unit, a programmable timer, a direct memory access (DMA) controller, an 2 EP 0 708 405 B1 interrupt controller, a real time clock, a video controller, a parallel/serial port and a PCMCIA controller. The CPU core, bus interface unit, DMA controller, programmable timer, serial port and video controller are each clocked by a distinct clock signal generated by a clock control unit embodied within the integrated processor. The clock control unit produces clock signals of distinct frequencies which drive the above-mentioned subsystems. The clock control unit operates 5 from a single oscillator crystal input. Coupled to receive the single oscillator crystal input within the clock control unit is a frequency synthesizer including one or more frequency multipliers and dividers. According to a preferred embod- iment, each frequency multiplier comprises a phase-locked loop circuit. The clock control unit synthesizes from the single input frequency multiple, distinct clock frequencies necessary to operate the various circuitry connected to the CPU local bus and peripheral interconnect bus. 10 [0012] The multiple phase-locked loop circuits are controlled according to a predetermined power management al- gorithm set forth in a power management unit (PMU). The power management unit is coupled to receive signals indic- ative of system activity. During periods of inactivity or at user-defined times selectable by software, the PMU changes from one power management state to another. A change in power management state generally results in a change in the assertions of various enable signals provided from the power management unit to the clock control unit. The enable 15 signals selectively control the enablement of the phase-locked loop circuits within the clock control unit and the gating of selected clock signals to conserve power. [0013] Other features and advantages of the embodiments will become apparent upon reading the following detailed description thereof and upon reference to the accompanying drawings in which: 20 Fig. 1 is a block diagram of an integrated processor system including a CPU core, a memory controller, a variety of peripheral devices, a clock control unit, and a related power management unit embodied upon a single monolithic chip according to one embodiment of the present invention; Fig. 2 is a block diagram of a clock control unit and associated input/output signals according to one embodiment 25 of the present invention; and Fig. 3 is a block diagram of a power management unit (PMU) and associated input/output signals according to one embodiment of the present invention; 30 Fig.