
Advancing nano-CMOS circuits simulation: convergence optimization, GPU parallelization and reliability analysis By Francesco Lannutti A Thesis submitted to the Department of Information Electronic and Telecommunication Engineering (DIET) University of Rome “La Sapienza” In partial fulfillment of the requirements for the degree of DOCTOR OF PHILOSOPHY Ing. Francesco Menichelli Prof. Alberto Sangiovanni-Vincentelli (Thesis Supervisor) (Second Thesis Supervisor) Abstract Advancing nano-CMOS circuits simulation: convergence optimization, GPU parallelization and reliability analysis By Francesco Lannutti Submitted to the Department of Information Electronic and Telecommunication Engineering (DIET) University of Rome “La Sapienza” In partial fulfillment of the requirements for the degree of DOCTOR OF PHILOSOPHY The idea of having an open-source circuit simulator originated in 60s at Berkeley from a team led by Prof. Ron Rohrer and Prof. Donald Pederson, who strongly believed that students could learn electronics in depth only through an instrument which let them participate actively in designing new circuits and analyzing existing ones (from Prof. Andrei Vladimirescu presentation at MOS-AK 2013). At the beginning, it was CANCER (Computer Analysis of Nonlinear Circuits, Excluding Radiation), then SPICE1 and 2 (Simulation Program with Integrated Circuit Emphasis), released multiple times during the subsequent years, both developed by Laurence Wolfgang (Larry) Nagel during his PhD, under the supervision of Prof. Donald Pederson. With the passing of time, SPICE had become so crucial that several semiconductor companies supported the program in house (e.g., Intel, TI, ST, and ATT) and added models for devices that were dependent on internally developed technology. Several small companies (e.g., Meta Software with HSPICE, OrCAD with PSPICE) modified SPICE slightly and sold their products in the market. Later on, Cadence Design Systems developed SPECTRE that was based on the research carried out by Kenneth Kundert and Jacob White at Berkeley which featured robust integration ADVANCING NANO-CMOS CIRCUITS SIMULATION I methods. SPICE and its derivatives are now the mostly used software in the world for accurate analog circuit simulation and standard cell characterization for digital flows. Fortunately, there are still open versions of SPICE that can be found on the web, among which the most known and used one is NGSPICE, an open-source version which integrates SPICE3, CIDER (which combines SPICE3 with an internal C-based device simulator, DSIM) and XSPICE developed at Georgia Tech. I have chosen NGSPICE for my research, because of the strong support by the community, which can provide invaluable user feedbacks during the research. Despite that, NGSPICE still suffers from coding and algorithmic point of view. While the first one comes from ancient inherits and treats about performances and memory occupancy, the second one is even worse, because it can generate quality of results issues, due to the usage of old algorithms in certain areas, and a usability problem, which makes NGSPICE difficult to be adopted in some research sectors, including new device Compact Models development in Verilog-A, without manually converting it in C code. My PhD research activity concerns the simulation of nano-scale CMOS integrated circuits and is focused on the following four topics: 1) Allowing the efficient simulation of very large circuits, including convergence techniques and the use of a GPU to speed up the analysis 2) Speeding up the simulation leveraging on parallelization algorithms 3) Implementing the Reliability Analysis to stress test the emergent technology nodes 4) Introducing algorithmic techniques to improve elaboration capacity and versatility and to allow the derivation of compact models that are needed to model new materials, new devices and new device effects During the first year of activity, I developed a new algorithm for convergence that attracted interest in the scientific community. It has been presented at MOS-AK 2013 in Bucharest in September 2013 and at PRIME2014 in Grenoble in July 2014 [1], where received the Silver Leaf Award by the conference committee. The results achieved during the second year sped up the simulation up to 3.74 times, by using the GPU acceleration and a novel approach to integrate the outputs of several independent models to only one Circuit Matrix and RHS. The obtained speedup implies decreasing the elapsed ADVANCING NANO-CMOS CIRCUITS SIMULATION II time, for example, from 1 hour, using the CPU version of NGSPICE, to 15 minutes, using GPU acceleration. During the third year, the Reliability Analysis has been successfully implemented in NGSPICE, generating a new framework that can leverage on state of the art aging models and can consider both the short term and long term behaviors. The fourth line of activity started during the end of the second year, continued all along the third year and unfortunately is not yet completed due to its complexity, yet it produced a Verilog- A Model Compiler with a complete chain of Lexer and Parser and a TCL user interface. ADVANCING NANO-CMOS CIRCUITS SIMULATION III Table of contents CHAPTER 1 - INTRODUCTION ............................................................................................................... 1 1.1 THE NGSPICE PROJECT .......................................................................................................................... 2 1.2 AUTOTOOLS TOOLCHAIN .......................................................................................................................... 3 1.3 THE AIM OF MY PHD ............................................................................................................................... 4 CHAPTER 2 - KLU – IMPROVEMENTS OVER MY MASTER’S THESIS RESULTS .......................................... 5 2.1 BINDING TABLE SORTING ......................................................................................................................... 6 2.2 KLU SUPPORT FOR ALL THE NGSPICE DEVICE MODELS ................................................................................. 7 2.3 KLU ENHANCEMENT IN SYMBOLIC FACTORIZATION ...................................................................................... 7 2.4 AN IDEA FOR THE PARALLELIZATION ........................................................................................................... 8 CHAPTER 3 - PERIODIC STEADY STATE ANALYSIS ................................................................................ 10 3.1 INTRODUCTION .................................................................................................................................... 10 3.2 STABILIZATION ..................................................................................................................................... 13 3.3 SHOOTING ........................................................................................................................................... 14 3.4 PERIODIC STEADY STATE ........................................................................................................................ 16 3.5 RESULTS .............................................................................................................................................. 17 CHAPTER 4 - A NOVEL CONVERGENCE ALGORITHM BASED UPON KCL VERIFICATION ......................... 20 4.1 THE NEWTON-RAPHSON METHOD .......................................................................................................... 24 4.2 THE STATE OF THE ART OF CONVERGENCE ALGORITHMS FOR CIRCUIT SIMULATION ............................................ 25 4.3 THE FALSE CONVERGENCE PHENOMENON ................................................................................................ 26 4.4 KCL VERIFICATION ................................................................................................................................ 26 4.5 F(VK) IN SPICE ..................................................................................................................................... 27 4.6 NODES CLASSIFICATION ......................................................................................................................... 28 4.7 CONTRIBUTIONS IN THE BSIM4 MODEL .................................................................................................... 28 4.8 A NEW HOMOTOPY METHOD FOR FASTER CONVERGENCE ............................................................................. 33 4.9 IMPLEMENTATION RESULTS .................................................................................................................... 35 4.10 LINEAR AND NON-LINEAR SEPARATION .................................................................................................. 36 CHAPTER 5 - CUSPICE – THE REVOLUTIONARY NGSPICE ON CUDA PLATFORM ................................... 43 5.1 INTRODUCTION .................................................................................................................................... 43 5.2 THE FERMI ARCHITECTURE ..................................................................................................................... 44 5.3 THE FERMI ARCHITECTURE MEMORY ACCESS ............................................................................................ 47 ADVANCING NANO-CMOS CIRCUITS SIMULATION IV 5.4 THE CUDA PLATFORM .........................................................................................................................
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