Engineering Specification for the KA43 Processor Module Revision 1.0 1–May–1989 COMPANY CONFIDENTIAL RESTRICTED DISTRIBUTION COPYRIGHT (c) 1989 by DIGITAL EQUIPMENT CORPORATION This information shall not be disclosed to non-Digital personnel or generally distributed within Digital. Distribution is restricted to persons authorized and designated by the responsible en- gineer or manager. This document shall not be left unattended, and when not in use shall be stored in a locked storage container. The information in this document is subject to change without notice and should not be construed as a commitment by Digital Equipment Corporation. Digital Equipment Corporation assumes no responsibility for any errors that may occur in this document. The information in this document does not describe any program or product currently available from Digital Equipment Corporation. Nor does Digital Equipment Corporation commit to imple- ment this specification in any program or product. Digital Equipment Corporation makes no commitment that this document accurately describes any product which it might ever make. Digital Equipment Corporation CONTENTS Preface . ........................................................... v Chapter 1 INTRODUCTION .............................................. 1 1.1 Scope of Document ................................................... 1 1.2 General Description .................................................. 1 1.3 Applicable Documents ................................................. 2 Chapter 2 KA43 ROM MEMORY ......................................... 3 2.1 System Board ROM .................................................. 3 2.2 Network Address ROM ................................................ 3 2.3 Option Board ROM ................................................... 4 Chapter 3 DC520 RIGEL CENTRAL PROCESSOR ........................ 5 3.0.1 Processor State ................................................... 5 3.0.1.1 General Purpose Registers ........................................ 5 3.0.1.2 Processor Status Longword ........................................ 6 3.0.1.3 Internal Processor Registers ....................................... 7 3.0.1.3.1 KA43 VAX Standard Internal Processor Registers . .................. 11 3.0.1.3.2 KA43 Unique Internal Processor Registers ......................... 12 3.0.2 Process Structure ................................................. 13 3.0.3 Data Types . ................................................... 13 3.0.4 Instruction Set . ................................................... 13 3.0.5 Memory Management . ........................................... 14 3.0.5.1 Translation Buffer . ........................................... 14 3.0.5.2 Memory Management Control Registers .............................. 15 3.0.6 Interrupts And Exceptions ........................................... 17 3.0.6.1 Interrupts . ................................................... 17 3.0.6.2 Exceptions . ................................................... 18 3.0.6.3 Information Saved On A Machine Check Exception . .................. 20 3.0.6.3.1 Byte Count ................................................. 20 3.0.6.3.2 "R" - Vax Restart Bit .......................................... 21 3.0.6.3.3 Machine Check Code Parameter ................................. 21 3.0.6.3.4 Contents of the RIGEL CPU’s internal VA Register .................. 23 3.0.6.3.5 Contents of the RIGEL CPU’s internal VIBA Register ................ 24 3.0.6.3.6 ICCS Register Bit<6> Contents .................................. 24 3.0.6.3.7 SISR Register Bits<15:0> Contents ............................... 24 3.0.6.3.8 Internal State Information . ................................... 24 3.0.6.3.9 Contents of the Shift Count (SC) Register .......................... 24 3.0.6.3.10 Contents of the Program Counter (PC) . .......................... 25 3.0.6.3.11 Contents of the Process Status Longword (PSL) . .................. 25 3.0.6.4 Machine Check Error Register (MCESR) IPR 38 ....................... 25 iii 3.0.6.5 System Control Block (SCB) ....................................... 25 3.0.6.6 The Hardware Halt Procedure . ................................... 27 3.0.7 System Identification ............................................... 29 3.0.7.1 System Identification Register (SID) IPR 62 .......................... 29 3.0.7.2 System Type Register (SYS_TYPE) ................................. 30 3.0.8 Accelerator Control and Status Register (ACCS) IPR 40 . .................. 30 Chapter 4 DC520 CPU REFERENCES .................................... 33 4.0.1 CPU References ................................................... 33 4.0.1.1 Instruction-Stream Read references ................................. 33 4.0.1.2 Data-Stream Read references . ................................... 33 4.0.1.3 Write References ................................................ 33 Chapter 5 DC523 RIGEL FPU ........................................... 35 5.0.1 Floating Point Accelerator Instructions ................................. 35 5.0.2 Floating Point Accelerator Data Types ................................. 35 5.0.3 Operand and Result Transfer ........................................ 36 5.0.4 Powerup State . ................................................... 36 Chapter 6 CACHE_MEMORY ............................................ 37 6.1 Cacheable References ................................................. 37 6.2 Primary Cache Overview . ........................................... 38 6.2.1 Primary Cache Organization ......................................... 38 6.2.2 Primary Cache Address Translation ................................... 39 6.2.3 Primary Cache Data Block Allocation .................................. 41 6.2.4 Primary Cache Behavior on Writes . ................................... 41 6.2.5 Primary Cache Internal Processor Registers . .......................... 41 6.2.5.1 Primary Cache Status Register (PCSTS) - IPR 127 . .................. 41 6.2.5.2 Error Address Register (PCERR) - IPR 126 . .......................... 44 6.2.5.3 Primary Cache Index Register (PCIDX) - IPR 125 ...................... 45 6.2.5.4 Primary Cache Tag Array Register (PCTAG) - IPR 124 .................. 46 6.2.6 Writing and Read the Primary Cache Tag Array .......................... 46 6.2.7 Primary Cache Error recovery ........................................ 46 6.2.8 Primary Cache Initialization ......................................... 47 6.2.9 Primary Cache Diagnostics .......................................... 47 6.2.10 Error Handling by the Primary Cache ................................. 47 6.2.10.1 Primary Cache Error Recovery . ................................... 50 6.3 Backup Cache Overview ............................................... 51 6.3.1 Backup Cache Organization ......................................... 52 6.3.2 Backup Cache Address Translation . ................................... 52 6.3.3 Backup Cache Data Block Allocation ................................... 53 6.3.4 Backup Cache Behavior on Writes . ................................... 54 iv 6.3.5 Maintaining Primary Cache Consistency ................................ 54 6.3.5.1 Vector Interface Error Status Register (VINTSR) - EPR 123 .............. 54 6.3.5.2 Cache Initialization . ........................................... 55 6.3.5.3 Diagnostics . ................................................... 55 Chapter 7 KA43 SYSTEM ERROR STATUS REGISTER .................... 57 Chapter 8 KA43 MISCELLANEOUS I/O REGISTERS ...................... 59 8.1 IO Reset Register (IORESET) ........................................... 59 8.2 Configuration and Test Register (CFGTST) ................................ 60 8.3 Halt Code Register (HLTCOD) .......................................... 61 8.4 Diagnostic Display Register (DIAGDISP) .................................. 61 8.5 Parity Control Register (PAR_CTL) . ................................... 61 8.6 Diagnostic Timer Register (DIAGTIME) ................................... 62 Chapter 9 KA43 INTERRUPT CONTROLLER ............................. 63 9.1 Interrupt Sources and Ranking ......................................... 64 9.2 Video Interrupt Select Register (VDC_SEL) ................................ 64 9.3 Interrupt Request Register (INT_REQ) ................................... 65 9.4 Interrupt Clear Register (INT_CLR) . ................................... 66 9.5 Interrupt Mask Register (INT_MSK) . ................................... 66 9.6 Interrupt Vector Generation . ........................................... 67 Chapter 10 KA43 TIME OF YEAR CLOCK ................................ 69 10.1 Battery Backup . ................................................... 69 10.2 Watch Chip Registers ................................................ 69 10.3 Control and Status Registers .......................................... 70 10.4 Time of Year Data ................................................... 72 10.5 Non-volatile RAM Storage . ........................................... 72 10.6 Initialization ....................................................... 72 Chapter 11 KA43 SERIAL LINE CONTROLLER ........................... 75 11.1 Line Usage ........................................................ 75 11.2 Diagnostic Terminal Connection ........................................ 75 11.3 Interrupts ......................................................... 76 11.4 Register Summary .................................................. 76 v 11.4.1 Control and Status Register (SER_CSR) ..............................