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Table of Contents Cadence Verilog Language and Simulation Table of Contents Cadence Verilog Language and Simulation Chapter 1 Getting Started Course Agenda................................................................................................................. 1-3 Course Schedule............................................................................................................... 1-7 Getting Help................................................................................................................... 1-13 Review ........................................................................................................................... 1-15 Chapter 2 Verilog Applications What Is a Hardware Description Language? ................................................................... 2-3 Why Use an HDL?........................................................................................................... 2-5 What is Verilog? .............................................................................................................. 2-7 Verilog History .......................................................................................................... 2-9 Verilog Applications................................................................................................ 2-11 Levels of Abstraction..................................................................................................... 2-13 Trade-Offs Among the Levels of Abstraction ......................................................... 2-15 Verilog-Supported Levels of Abstraction................................................................ 2-17 The Behavioral Level............................................................................................... 2-19 The RTL Level......................................................................................................... 2-21 The Structural Level ................................................................................................ 2-23 One Language for All Levels................................................................................... 2-25 Summary........................................................................................................................ 2-27 Review ........................................................................................................................... 2-29 Chapter 3 Introduction to Cadence Simulators Simulation Algorithms..................................................................................................... 3-3 The Time Wheel in Event-Based Simulation .................................................................. 3-5 Event Simulation of a Verilog Model.............................................................................. 3-7 The Cadence Verilog Simulators..................................................................................... 3-9 Interpretive Versus Compiled-Code Simulation............................................................ 3-11 Verilog-XL Can Interpret Behavioral Source.......................................................... 3-13 NC-Verilog Precompiles All Source Code.............................................................. 3-15 Verilog Language Support............................................................................................. 3-17 Invoking Verilog-XL and NC-Verilog .......................................................................... 3-19 Verilog-XL and NC-Verilog Differences ...................................................................... 3-21 The Simvision Waveform Viewer ................................................................................. 3-25 February 18, 2002 Cadence Design Systems, Inc. iii Cadence Verilog Language and Simulation Table of Contents The Signalscan Waveform Display ............................................................................... 3-27 The SHM Waveform Database...................................................................................... 3-31 Probing Signals with $shm_probe ........................................................................... 3-33 Related Products ............................................................................................................ 3-35 Summary........................................................................................................................ 3-37 Review ........................................................................................................................... 3-39 Chapter 4 A Sample Design Key Language Features.................................................................................................... 4-3 The Verilog Module................................................................................................... 4-5 Module Ports.............................................................................................................. 4-7 Module Instances ....................................................................................................... 4-9 A Simple and Complete Example.................................................................................. 4-11 Device Under Test ................................................................................................... 4-13 Testbench ................................................................................................................. 4-15 The Value Change Dump (VCD) .................................................................................. 4-27 Dumping Signals with $dumpvars........................................................................... 4-29 Summary........................................................................................................................ 4-31 Review ........................................................................................................................... 4-33 About Lab 1 ................................................................................................................... 4-35 Chapter 5 Lexical Conventions in Verilog White Space and Comments ............................................................................................ 5-3 Integer and Real Numbers ............................................................................................... 5-5 String Constants............................................................................................................... 5-7 Identifiers ......................................................................................................................... 5-9 Escaped Identifiers................................................................................................... 5-11 Special Language Tokens .............................................................................................. 5-13 System Tasks and Functions.................................................................................... 5-15 Specifying Delay...................................................................................................... 5-17 Compiler Directives......................................................................................................