materials Communication Facile Process for Surface Passivation Using (NH4)2S for the InP MOS Capacitor with ALD Al2O3 Jung Sub Lee 1, Tae Young Ahn 1,* and Daewon Kim 2,* 1 Department of Orthopaedic Surgery and Medical Research Institute, Pusan National University Hospital, 179 Gudeok-ro, Seo-gu, Busan 49241, Korea; [email protected] 2 Department of Electronic Engineering, Institute for Wearable Convergence Electronics, Kyung Hee University, 1732 Deogyeong-daero, Giheung-gu, Yongin 17104, Korea * Correspondence: [email protected] (T.Y.A.); [email protected] (D.K.) Received: 9 June 2019; Accepted: 25 November 2019; Published: 27 November 2019 Abstract: Ammonium sulfide ((NH4)2S) was used for the passivation of an InP (100) substrate and its conditions were optimized. The capacitance–voltage (C–V) characteristics of InP metal-oxide-semiconductor (MOS) capacitors were analyzed by changing the concentration of and treatment time with (NH4)2S. It was found that a 10% (NH4)2S treatment for 10 min exhibits the best electrical properties in terms of hysteresis and frequency dispersions in the depletion or accumulation mode. After the InP substrate was passivated by the optimized (NH4)2S, the results of x-ray photoelectron spectroscopy (XPS) and the extracted interface trap density (Dit) proved that the growth of native oxide was suppressed. Keywords: III–V semiconductor; indium phosphide (InP), Al2O3; (NH4)2S; sulfur passivation 1. Introduction As silicon-based, complementary metal-oxide-semiconductor (CMOS) technology has been approaching its fundamental limits, III–V semiconductors have been focused on as alternative channel materials due to their high electron mobility. In particular, indium phosphide (InP) is considered one of the promising materials due to its larger band gap than silicon (~1.34 eV), which results in low off-state leakage current and high breakdown field [1–3]. In addition, InP is preferred to a barrier layer between the gate oxide and the InxGa1 xAs channel [4]. Despite these advantages, the poor − interfacial quality between a high-k dielectric and an InP substrate compared to SiO2 and Si is still a major obstacle to overcome before high-performance MOS field-effect-transistors (MOSFETs) can be realized. Thus, every endeavor to keep the InP substrate clear of the native oxide growth and external contamination prior to deposition of the high-K dielectric is required for a reduction of Dit. For this purpose, ex situ cleaning methods using wet chemicals, such as HCl, H2SO4, NH4OH, and HF, have consistently been developed [5]. Various works have been done for the enhancement of the interfacial quality over the last few decades [6–8]. Recently, Cuypers et al. reported that sulfur passivation by (NH4)2S was useful for suppressing unwanted effects arising from pre-existing defects and the rapid re-oxidation of the surface after wet chemical cleaning [9]. As the group VI element, sulfur and oxygen have the same number of valence electrons; however, the electronegativity of sulfur is lower than that of oxygen. Hence, the interface of In–S become stable so that the formation of the native oxide can be effectively inhibited. To take advantage of this feature, (NH4)2S has widely been employed [1–3,10–13]. However, comprehensive analyses regarding the process parameters used in sulfur passivation which affect the InP MOSFETs remain insufficient. In this work, the conditions of (NH4)2S passivation were optimized to enhance the performance of the device. The electrical characteristics of an InP MOS capacitor (MOSCAP) were investigated Materials 2019, 12, 3917; doi:10.3390/ma12233917 www.mdpi.com/journal/materials Materials 2019, 12, 3917 2 of 7 Materials 2018, 11, x FOR PEER REVIEW 2 of 7 whileThen, varyingthe chemical the passivation properties conditions of the sulfur-passiva of (NH4)2S,ted in thisinterface case thewith concentration the optimized and conditions treatment were time. Then,compared the chemicalwith those properties of a non-passiv of the sulfur-passivatedated interface. Furthermore, interface with the the Dit optimizeddistribution conditions across the were InP comparedenergy bandgap with those was of extracted a non-passivated using a interface.conductance Furthermore, method [14–17] the Dit distributionin order to acrossevaluate the InPthe energyinterfacial bandgap quality, was which extracted affects using the performances a conductance of method InP MOSFETs. [14–17] in order to evaluate the interfacial quality, which affects the performances of InP MOSFETs. 2. Experimental 2. Experimental MOSCAPs were fabricated on an undoped InP (100) wafer with an n-type carrier concentration of 5 ×MOSCAPs 1015 cm−3. wereInitially, fabricated the substrates on an undoped were cleaned InP (100) with wafer a 1% with HF an solution n-type carrierfor 5 min, concentration after which of 15 3 5they10 werecm treated− . Initially, with the(NH substrates4)2S at concentrations were cleaned of with 1%, a 5%, 1% HF10%, solution and 22% for which 5 min, were after whichdiluted they by × weredeionized treated H2 withO for (NH 10 min4)2S at concentrationsroom temperature of 1%, (300 5%, K). 10%, Other and substrates 22% which were were treated diluted with by deionized the fixed Hconcentration2O for 10 min of at 10% room (NH temperature4)2S for 5 (300min, K).10 Othermin, and substrates 30 min. were As treatedthe gate with oxide, the 7 fixed nm concentrationof Al2O3 was ofdeposited 10% (NH on4) 2theS for substrate 5 min, 10 at min, a temperature and 30 min. of As 150 the °C gate by oxide, means 7 nmof atomic of Al2 Olayer3 was deposition deposited (ALD) on the substrateafter a rinse at aby temperature water was perf of 150ormed.◦C by In means the ALD of atomic process, layer trimethylaluminum deposition (ALD) (TMA) after a and rinse H by2O waterwere wassequentially performed. supplied In the under ALD process, purging trimethylaluminum with N2 during each (TMA) deposition and H 2cycle.O were For sequentially a gate electrode, supplied 10 undernm of purgingNi and 100 with nm N2 ofduring Au were each deposited deposition using cycle. a For thermal a gate evaporator electrode, 10through nm of Nia shadow and 100 mask. nm of AuAfterwards, were deposited the MOSCAPs using a thermalwere annealed evaporator with throughambient a gas shadow (4% H mask.2/96% Afterwards,N2) at 400 °C the for MOSCAPs30 min. were annealed with ambient gas (4% H2/96% N2) at 400 ◦C for 30 min. 3. Discussion and Results 3. Discussion and Results The structural properties of the Au/Ni/Al2O3/InP samples were characterized by high-resolution transmissionThe structural electron properties microscopy of the Au(HR-TEM)/Ni/Al2O 3us/InPing samples a field-emission were characterized transmission by high-resolution microscope transmissionoperated at 300 electron kV (Tecnai microscopy G2 F30). (HR-TEM) In order using to study a field-emission the bonding transmission status at the microscope Al2O3/InP interface, operated atex 300situ kV X-ray (Tecnai photoelectron G2 F30). In spectroscopy order to study (X thePS) bonding was analyzed status using at the Ala monochromated2O3/InP interface, Al ex Κα situ (1486.7 X-ray photoelectroneV) source with spectroscopy a base pressure (XPS) was in analyzedthe mid-10 using−10 Torr a monochromated range. Capacitance-voltage Al Kα (1486.7 (C–V) eV) source and 10 withconductance–voltage a base pressure in (G–V) the mid-10 measurements− Torr range. were Capacitance-voltagecarried out using an (C–V)E4980A and precision conductance–voltage LCR meter at (G–V)room temperature. measurements were carried out using an E4980A precision LCR meter at room temperature. A schematic of thethe MOSCAPMOSCAP isis shownshown inin FigureFigure1 a.1a. AlAl22O3 was deposited over the entire InP substrate. Afterwards, patterned Ni and Au were deposited through a shadow mask which had holes with a diameter of 300 µμm. Figure 1 1bb showsshows aa cross-sectionalcross-sectional HR-TEMHR-TEM imageimage ofof thethe MOSCAPMOSCAP onon thethe InP substrate, whichwhich waswas treatedtreated withwith thethe 10%10% (NH(NH44))22S solution for 10 min. The TEM image indicates that thethe ALDALD AlAl22O3 has a uniform thickness andand anan amorphousamorphous structure.structure. Moreover, an abrupt interface was created withoutwithout thethe growthgrowth ofof thethe nativenative oxide.oxide. Figure 1. (a) Device schematic for the InP metal-oxide-semiconductormetal-oxide-semiconductor (MOS) capacitor. (b) HR-TEM image of 7 nm thick AlAl2O3 onon the the InP InP (100) (100) substrate. substrate. Figure 2a–e shows the C–V characteristics of the devices treated with diluted (NH4)2S solutions at different concentrations. Three issues exist in all of the curves. First, the accumulation capacitance cannot reach the theoretical value of the oxide capacitance, which is calculated according to the actual thickness of the gate dielectric. This phenomenon originates from the low density of states (DOS) of the InP substrate above the conduction band. Secondly, there is frequency dispersion in the depletion Materials 2019, 12, 3917 3 of 7 Figure2a–e shows the C–V characteristics of the devices treated with diluted (NH 4)2S solutions at different concentrations. Three issues exist in all of the curves. First, the accumulation capacitance cannot reach the theoretical value of the oxide capacitance, which is calculated according to the actual thicknessMaterials 2018 of, 11 the, x gateFOR PEER dielectric. REVIEW This phenomenon originates from the low density of states (DOS)3 of of 7 the InP substrate above the conduction band. Secondly, there is frequency dispersion in the depletion mode,mode, an indicator of of the the level level of of D Dit,it which, which is isan an important important characteristic characteristic in terms in terms of enhancing of enhancing the theperformance performance of MOSFETs. of MOSFETs. Lastly, Lastly, there there is also is alsofrequency frequency dispersion dispersion in the in accumulation the accumulation mode. mode. This Thisis associated is associated with with conductive conductive losses, losses, which which are are mostly mostly caused caused by by border border traps traps located located in in the gategate dielectricdielectric near the interface [16,18,19].