5 4 3 2 1 DATE Description Modify By 2012/8/1 Initial Jacky_Kuo 2012/11/5 1.DEL all circuit related to WB40. D 2.Page3, pull down U2 pin44 with a 10k ohm resister - R163. D 3.Page4, modified Q1 to PMOS. 4.Page6, Change R96, R100, R101, R102, R104, R106, R107, R108, R110 to 1k ohm. 5.Page7, removed codec circuit and reserved a 10pins header. 6.Page7, modified net name "3V3_PCM" to "+3V3_PCM". Jacky_Kuo 7.Page8, add a 3.3V supply rail for single PHY circuit. 8.Page8, added a jumper CON66 for "+3V3_ETH" rail. 9.Page8, change the U26' VIN from "+3V3" to "+5V". 10.Page8, added a jumper CON67 for "+3V3" rail. C 11.Page9, fixed D24 and C151 polarity. C 12.Page9, added a CON72 for test fixture power On/Off switch. 2012/12/5 1.Page6, change D10 footprint to correct LED type. Jacky_Kuo 2.Page8, Del. Q2 & Q3 2012/12/20 1.Page9, change D23 symbol to meet SOD-323 footprint. 2.Page9, change CON72 to 1x3 pin header. Jacky_Kuo 3.Page9, change U27 to RT7247B 4.Page2, correct J1 pin number to meet WB45 J4 2013/01/07 1.Page6, pull down R99 to GND for the U17 write operation. Jacky_Kuo B B 2.Page7, change CON52 to 1x6 pin header with 2.0mm pitch. 3.Page7, change CON65 pin assignment to meet CODEC board. 2013/05/31 1.Page6, modifies U16 supplies rail from +3V3 to +1V8B Jacky_Kuo 2013/06/19 1.Page8, modifies U26 VIN supplies rail from +5Vto +3V3 Jacky_Kuo ( For the both antenna holes which they're need to add hole ring with solder-mask layer) 2013/08/29 1.Page4, modified R45 and R46 to 0 ohm. Jacky_Kuo Laird Technology A A 5F, No.257, Dong Sec. 1 Guangming 6th Rd., Zhubei City, Hsinchu County, Taiwan Title BB45NBT Size Document Number Rev A4 History 1.0 Date: Thursday, August 29, 2013 Sheet 1of 9 5 4 3 2 1 5 4 3 2 1 BB PCB PIN OUT (TOP VIEW) PIN-79 PIN-1 CON3 CON1 CON2 STAND-OFF (F40M20) STAND-OFF (F40M20) STAND-OFF (F40M20) D D GND GND GND 1 1 1 GND GND GND PIN-80 PIN-2 J1 3V3_BU 2 1 3V3_ANA +3V3_BU 2 1 +3V3_ANA GND 4 3 GND 4 3 AIO-1 WKUP 8 6 5 VBUS_EN 4 WKUP AIO-0 6 5 C1 C2 4 8 7 SHDN SHDN 8 C3 C4 VBUS_SENSE AIO-2 10 8 7 9 AIO-3 10 uF 0.01 uF 4 OVER_CURRENT 10 9 AIO-3 6 0.01 uF 10 uF GND 12 11 IRQ IRQ 6 EMDC 14 12 11 13 3 EMDC 14 13 GND C GND 16 15 ETXEN ETXEN 3 C ETX1 18 16 15 17 ETX0 3 ETX1 ETX0 3 GND GND ERX0 20 18 17 19 ERXER GND GND ERX0 3 ERXER 3 ERX1 22 20 19 21 R174 3 ERX1 GND 0 ECRSDV 24 22 21 23 3 ECRSDV EREF_CLK 3 EMDIO 26 24 23 25 3 EMDIO GND 28 26 25 27 TWD1 GND TWD1 6 30 28 27 29 TWCK1 C162 +1V8 30 29 TWCK1 6 GND 32 31 GND NOPOP GPIO-1 34 32 31 33 GPIO-0 6 GPIO-1 34 33 GPIO-0 6 C5 C6 GPIO-3 36 35 GPIO-2 6 GPIO-3 36 35 GPIO-2 6 GND 38 37 GND GND 10 uF 0.01 uF URTS3 40 38 37 39 URXD3 5 URTS3 URXD3 5 UCTS3 42 40 39 41 UTXD3 5 UCTS3 42 41 UTXD3 5 GND 44 43 GND URTS0 46 44 43 45 URXD0 5 URTS0 URXD0 5 GND GND UCTS0 48 46 45 47 UTXD0 5 UCTS0 48 47 UTXD0 5 GND 50 49 GND SPI0_MISO 52 50 49 51 SPI0_CSn1 6 SPI0_MISO SPI0_CSn1 6 SPI0_MOSI 54 52 51 53 6 SPI0_MOSI GND SPI0_CSn0 56 54 53 55 SPI0_CLK B 6 SPI0_CSn0 SPI0_CLK 6 B 58 56 55 57 GND 58 57 GND +3V3 60 59 DRXD DRXD 6 62 60 59 61 DTXD +3V3 62 61 DTXD 6 C7 C8 GND 64 63 GND NRST 66 64 63 65 HHSDPA 8 NRST HHSDPA 4 10 uF 0.01 uF WOW 68 66 65 67 HHSDMA 6 WOW HHSDMA 4 WIFI_GPIO 70 68 67 69 6 WIFI_GPIO 70 69 GND GND 72 71 GND PCM_IN 74 72 71 73 PCM_CLK PCM_IN 7 74 73 PCM_CLK 7 GND GND GND 76 75 GND PCM_OUT 78 76 75 77 PCM_SYNC 7 PCM_OUT PCM_SYNC 7 80 78 77 79 GND 80 79 GND 55560-0807 Laird Technology A A 5F, No.257, Dong Sec. 1 Guangming 6th Rd., Zhubei City, Hsinchu County, Taiwan Title BB45NBT Size Document Number Rev A4 B2B Connector 1.0 Date: Thursday, August 15, 2013 Sheet 2of 9 5 4 3 2 1 5 4 3 2 1 R3 10K +3V3A_ETH +3V3D_ETH U2 C13 LED and PHY address Configuration EMDC R6 27 25 36 3V3A_ETH GND Set IP101A EMDIO R7 27 26 MDC AVDD33 8 REGIN This schematic sets PHY address to to RMII Mode ETX0 R8 27 6 MDIO REGIN 32 REGOUT ETX1 R9 27 5 TXD0 REGOUT 0.1 uF 00001 4 TXD1 29 +3V3D_ETH +3V3D_ETH 3 TXD2 AGND 35 ETXEN R4 27 2 TXD3 AGND TX_EN C14 EREF_CLK R5 27 7 R11 10K ECRSDV R10 27 22 REF_CLK GND R15 PHYAD0/LED0 CRS_DV GND ERX0 R13 27 21 28 GND R12 ERX1 R14 27 20 RXD0 ISET D1 D IP101A R16 D 10K C163 19 RXD1 6.19K 2 1 LINK 0.1 uF RXD2 NOPOP 18 560 R17 27 16 RXD3 31 MDI_RP HT-F194NB5 HARVATEK GND C50M_O MDI_RP ECOL 1 30 MDI_RN R18 10K 23 COL MDI_RN PHYAD1/LED1 ERXER R19 0 24 CRS/LEDMOD D2 X1_INPUT 46 RX_ER 33 MDI_TN R21 X2_OUTPUT 47 X1 MDI_TN 34 MDI_TP 10/100 [ L: 10M] 1 2 DUPX X2 MDI_TP R20 560 2.2K +3V3D_ETH 27 TP5 SMD TEST_ON 3V3_ETH 14 R23 10K * R22 10K 48 DVDD33 37 AN_ENA TP6 SMD PHYAD2/LED2 INTR AN_ENA 38 DPLX TP7 SMD R24 D3 GND PHYAD0/LED0 9 DPLX 39 SPD GND R25 PHYAD1/LED1 10 PHYAD0/LED0 SPD 40 RPTR TP8 SMD 1 2 10M ACT PHYAD1/LED1 RPTR NOPOP 10K PHYAD2/LED2 12 41 APS TP9 SMD 560 PHYAD3/LED3 13 PHYAD2/LED2 APS 43 ISOL TP10 SMD CON14 R163 PHYAD4/LED4 15 PHYAD3/LED3 ISOL 44 MII/SNIB NOPOP PIN-HEADER-2.0mm-6 GND R26 10K EMDC 1 PHYAD4/LED4 MII/SNIB PHYAD3/LED3 2 EMDC 10K EMDIO 2 1 11 42 2 EMDIO +3V3D_ETH D4 EREF_CLK 3 2 17 DGND RESET_N 2 EREF_CLK R28 ETX0 4 3 45 DGND R27 10K 1 2 100M ACT 2 ETX0 ETX1 5 4 DGND 2 ETX1 560 ETXEN 6 5 C15 2 ETXEN 6 GND IP101ALF R29 10K Pin48 could be short 3V3_ETH if 0.1 uF PHYAD4/LED4 D5 ERXER 1 CON17 interrupt funtion is not used. 2 ERXER R30 C ERX0 2 1 NOPOP PIN-HEADER-2.0mm-6 GND 1 2 COL C 2 ERX0 ERX1 3 2 2 ERX1 560 ECRSDV 4 3 2 ECRSDV 4 5 Hardwire Configuration network: R31 27 ENRST ENRST 8 6 5 6 1. This configuration shows GND Enable: Auto negotiation, Full duplex, 100Mbps, C16 LED0 LED1 LED2 LED3 LED4 Link Down Power Saving, RMII interface Link Dupx 10Act 100Act COL Disable: Isolate, Repeater mode 0.1 uF 2. These senven configuration pins could be connected to VDD or GND directly. GND * Pull down U2 pin4 for RMII clock source 25MHz. B B +3V3_ETH +3V3A_ETH +3V3_ETH +3V3D_ETH L2 L1 MLB-160808-0220P-N2 MLB-160808-0220P-N2 C17 ** GND C18 C19 0.1 uF J0011D01BNL 10 uF 0.1 uF C22 12 0.1 uF RLED+ GND 11 R34 GND GND RLED- 13 0 As close to IP101A GND GND 10 14 0 GND As close to IP101A 9 LLED- GND Pin14 as possible LLED+ R35 Pin36 as possible R36 R33 49.9 49.9 GND 8 7 GND 15 NC NC 16 use 25M crystal MDI_RN 6 NC 5 RD- MDI_RP 3 CT L3 RD+ R32 R37 MLB-160808-0220P-N2 MDI_TN 2 X2_OUTPUT Y1 X1_INPUT REGOUT REGIN 4 TD- 25MHz MDI_TP 1 CT 0 * * TD+ 27 1 3 C23 C24 C25 C26 J2 0.1 uF 22 uF 0.1 uF 0.01 uF A 2 4 A C20 C21 R38 R39 49.9 49.9 33 pF 33 pF GND GND GND GND Laird Technology As close to IP101A As close to IP101A R40 REGOUT 5F, No.257, Dong Sec. 1 Guangming 6th Rd., GND Pin32 as possible Pin8 as possible C27 C28 C29 0 Zhubei City, Hsinchu County, Taiwan GND GND 0.1 uF 0.01 uF 0.1 uF Title BB45NBT CRYSTAL ** Bead should be placed as close to IP101A GND Size Document Number Rev as close as to chip as possible and in the same side as IP101A. GND A3 SinglePHY_ETH 1.0 Date: Thursday, August 15, 2013 Sheet 3of 9 5 4 3 2 1 5 4 3 2 1 +5V 2.0mm PIN HEADER C30 HIGH ENABLE CON19 GND VUSB_VBUS0 PIN-HEADER-2P0mm-2 D D U3 2 1 0.1 uF 2 6 2 1 3 IN OUT 7 2 3.3V IN OUT 8 D6 C34 GPIO-0 4 OUT 220uF 2 VBUS_EN C31 C32 C33 PJSD05 EN 5 +3V3B 1 OC 10 uF 0.01 uF 0.1 uF 1 GND GPAD AIO-0 R41 10K 9 C35 R42 GND GND GND GND GND GND GND GND 560 GND 0.1 uF TPS2051BDGN 1 RED R44 D7 10K +3.3V R43 (VBUS_SENSE) 2 VBUS_SENSE C C 2 15K AIO-3 R45 2 22K C36 AIO-2 HARVATEK HARVATEK HT-F194USD-DT HT-F194USD-DT S 1 15pF 2 OVER_CURRENT G Q1 OC: "L" SMG2301P D GND GND P-MOS 3 GND USB0 Port (Host & Device) USB OVER CURRENT MINI USB AB-type RECEP RIGHT ANGLE B INDICATOR CON20 B MUSBB5F0301G30R L4 R46 4 1 USB0_CONN_DM 1 6 2 HHSDMA VBUS CGND 0R 2 7 R47 3 2 USB0_CONN_DP 3 D- CGND 2 HHSDPA D+ 0R 4 8 5 GND CGND 9 ACM2012H-900-2P-T00 TDK GND CGND 3 2 C37 C38 U4 1000 pF 1000 pF D- D+ PJDLC05 2KV 2KV GND GND GNDUSB0 GNDUSB0 1 Laird Technology A GND GNDUSB0 A 5F, No.257, Dong Sec.