St. Cloud State University theRepository at St. Cloud State Culminating Projects in Computer Science and Department of Computer Science and Information Information Technology Technology 5-2018 Parallel Implementation of AES using XTS Mode of Operation Muna Shrestha St. Cloud State University, [email protected] Follow this and additional works at: https://repository.stcloudstate.edu/csit_etds Part of the Computer Sciences Commons Recommended Citation Shrestha, Muna, "Parallel Implementation of AES using XTS Mode of Operation" (2018). Culminating Projects in Computer Science and Information Technology. 21. https://repository.stcloudstate.edu/csit_etds/21 This Starred Paper is brought to you for free and open access by the Department of Computer Science and Information Technology at theRepository at St. Cloud State. It has been accepted for inclusion in Culminating Projects in Computer Science and Information Technology by an authorized administrator of theRepository at St. Cloud State. For more information, please contact [email protected]. Parallel Implementation of AES Using XTS Mode of Operation by Muna Shrestha A Starred Paper Submitted to the Graduate Faculty of St. Cloud State University in Partial Fulfillment of the Requirements for the Degree Master of Science in Computer Science May, 2018 Starred Paper Committee: Andrew A. Anda Jie H. Meichsner Mehdi Mekni 2 Abstract Data encryption is essential for protecting data from unauthorized access. The Advanced Encryption Standard (AES), among many encryption algorithms, is the most popular algorithm currently employed to secure static and dynamic data. There are several modes of AES operation. Each of these modes defines a unique way to perform data encryption. XTS mode is the latest mode developed to protect data stored in hard-disk-like sector-based storage devices. A recent increase in the rate of data breaches has triggered the necessity to encrypt stored data as well. AES encryption, however, is a complex process. As it involves a lot of computations, encrypting huge amount of data would undoubtedly be computationally intensive. Parallel computers have been used mostly in high-performance computation research to solve computationally intensive problems. Parallel systems are currently gaining popularity configured as general purpose multi-core system, even at a desktop level. Several programming models have been developed to assist the writing of parallel programs, and some have already been used to parallelize AES. As a result, AES data encryption has become more efficient and applicable. The message passing model is a popular parallel communication/synchronization model with an early origin. Message Passing Interface (MPI) is the first standardized, vendor- independent, message passing library interface that establishes a portable, efficient, and flexible standard for message passing during computation. Therefore, this paper describes an implementation of AES using XTS mode in parallel via MPI. 3 Table of Contents Page List of Tables ........................................................................................................................ 6 List of Figures ....................................................................................................................... 7 Chapter 1. Introduction ............................................................................................................... 8 2. Parallel Programming with MPI ............................................................................... 12 2.1 Parallel Computer .............................................................................................. 12 2.2 Design of a Parallel Program ............................................................................. 13 2.2.1 Stage 1–Partitioning ............................................................................... 13 2.2.2 Stage 2–Communication ........................................................................ 14 2.2.3 Stage 3–Agglomeration .......................................................................... 15 2.2.4 Stage 4–Mapping .................................................................................... 15 2.3 Implementation of a Parallel Program ............................................................... 16 2.3.1 Parallel Programming Model ................................................................. 17 2.3.2 Writing a Parallel Program Using MPI .................................................. 18 2.4 Communication in MPI Programming ...................................................................... 21 2.4.1 Barrier ..................................................................................................... 23 2.4.2 Broadcast ................................................................................................ 23 2.4.3 Gather ..................................................................................................... 23 2.4.4 Scatter ..................................................................................................... 23 2.4.5 All-to-All ................................................................................................ 24 4 Chapter Page 2.4.6 Reduce .................................................................................................... 24 2.4.7 Prefix ...................................................................................................... 24 3. AES and XTS Mode of Operation ............................................................................ 25 3.1 Background ....................................................................................................... 25 3.2 XTS Mode of Operation .................................................................................... 26 3.2.1 AES using XTS Mode of Operation (XTS-AES) .................................. 27 3.2.2 Ciphertext Stealing ................................................................................. 30 3.3 Advanced Encryption Standard (AES) .............................................................. 31 3.3.1 Substitute Bytes ...................................................................................... 33 3.3.2 Shift Rows .............................................................................................. 35 3.3.3 Mix Columns .......................................................................................... 35 3.3.4 Add Round Key ...................................................................................... 36 3.4 Key Expansion .................................................................................................. 36 3.5 Multiplication in Galios Field (GF92 n)) ........................................................... 38 4. Methodology ............................................................................................................. 40 4.1 Design of Parallel XTS-AES Algorithm ........................................................... 40 4.2 Implementation of Parallel XTS-AES Algorithm ............................................. 45 4.2.1 Task Mapping ......................................................................................... 45 4.2.2 Key Expansion ....................................................................................... 46 4.2.3 Input Data Processing ............................................................................. 47 4.2.4 Single Block Operation .......................................................................... 48 5 Chapter Page 4.2.5 AES Encryption ...................................................................................... 49 4.2.6 Substitute Bytes ...................................................................................... 49 4.2.7 Shift Rows .............................................................................................. 49 4.2.8 Mix Columns .......................................................................................... 50 4.2.9 Add Round Keys .................................................................................... 50 4.2.10 Ciphertext Stealing ................................................................................ 50 4.2.11 Multiplication in GF(2128) ..................................................................... 51 4.2.12 Handle Result ........................................................................................ 51 4.2.13 Synchronize Processors ......................................................................... 51 5. Result and Analysis ................................................................................................... 52 6. Conclusion ................................................................................................................ 57 References ............................................................................................................................ 59 Appendix ............................................................................................................................ 61 6 List of Tables Table Page 1. Block Cipher Modes of Operation ............................................................................ 26 2. XTS-AES Mode ........................................................................................................ 31 3. AES S-box ................................................................................................................ 33 4. AES Inverse S-box ...................................................................................................