IIIIUSOO5778241A United States Patent 119 11) Patent Number: 5,778,241 Bindloss et al. 45 Date of Patent: Jul. 7, 1998 54 SPACE VECTOR DATA PATH 0464601 1/1992 European Pat. Off.. 213672 971984 United Kingdom. (75) Inventors: Keith M. Bindloss; Kenneth E. Garey. both of Irvine; George A. Watson, OTHER PUBLICATIONS Fuerton; John Earle. Tustin, all of Calif. Intel i860TM 64-Bit Microprocessor Programmer's Refer ence Manual 1989, Chapter 1. Architectural Overview, pp. 73) Assignee: Rockwell International Corporation, 1-1-1-6. Newport Beach, Calif. New PA-RISC Processor Decodes MPEG Video, HP's PA-710OLC Uses New Instructions to Eliminate Decoder 21 Appl. No.: 630,231 Chip, Microprocessor Report Jan. 24, 1994, pp. 16-17. 22 Filed: Apr. 10, 1996 it Primary Examiner-John E. Harrity Related U.S. Application Data Attorney, Agent, or Firm-William C. Cray; Philip K. Yu 63 Continuation of Ser. No. 238,558, May 5, 1994, abandoned. 57 ABSTRACT (51) int. Cl. ... G06F 15/80 A space vector data path for integrating SIMD scheme into (52) U.S. Cl. ................. 395/800,2; 395/570; 364/232.21; a general-purpose programmable processor. The program 364/231.9; 364/DIG. 1 mable processor uses a mode field in each instruction to 58) Field of Search ..................................... 395/800, 375. specify, for each instruction, whether an operand is pro 395/800.2, 800.02.570; 364/232.21, 231.9, cessed in either one of vector or scalar modes. The pro D.G. 1 grammable processor also has a plurality of sub-processing units for receiving the operand and, responsive to an instruc (56) References Cited tion as specified by the mode field in each instruction, for processing the operand in either one of the vector or scalar U.S. PATENT DOCUMENTS modes, wherein the vector mode indicates to the plurality of 4,161,784 7/1979 Cushing et al. ........................ 364,748 sub-processing units that there are a plurality of elements 4,481,580 1/1984 Martin et al. .. ... 395,309 within the operand and the scalar mode indicates to the 4,777593 10/1988 Yoshida. 3950 plurality of sub-processing units that there is but one ele 4,928.238 5/1990 Sekiguchi. 395/800 ment within the operand. For the vector mode, each element 5,239.6545212,777 8/19935/1993 Ing-SimmonsGove et al. ............... et al. ................ 395/375osso 1s processedd by one of the sub-processingp g units concurrently 5.247,696 9/1993 Booth ........................ go to generate a vector result. For the scalar mode, the sub 5,396,625 3/1995 Parkes ... ... 395/600 elements of the one element operand are processed by the 5,475.856 12/1995 Kogge ..................................... 395/800 sub-processing units concurrently but independently to gen erate a scalar result. FOREIGN PATENT DOCUMENTS 0395348 10/1990 European Pat. Off. 7 Claims, 32 Drawing Sheets - 1OO PROGRAM & DATA STORA GE UN NSTRUCT ONS NST. 130 OPERAND ACQUESTON 110 121 122 ALU MAC NS. FETC / DECODER / SEQUENCER 123 Y 124 N SHIFTER Logic U.S. Patent Jul. 7, 1998 Sheet 1 of 32 5,778,241 MAN SECUENCER N t ----------S PE 11 PE 2 - PE1 --PE 12 PE 22 PE2 NOTE; INTER CONNECTION FOR DATA & PE'S NOT SHOWN \--- A -v- INSTRUCT ON BUS F. G. 1C (Prior Art) CPU LOCAL -base MEMORY \- V FG 1b. (Prior Art) U.S. Patent Jul. 7, 1998 Sheet 2 of 32 5,778,241 1OO PROGRAM & DATA STORA GE UNIT INSTRUCTIONS NST. OPERAND ACQUIST ON 110 121 122 NST. (AY FETCH / DECODER / SEQUENCER 1231) 124 N sHIFTER LOGIC F. G. 2 U.S. Patent Jul. 7, 1998 Sheet 3 of 32 5,778.241 - 202 s/U X51...XO YJ1...YO - 32-BIT ADDER 2O1 - 2 OO 2O5 S31...SO F.G. 5 O (Prior Art) s/u U15... UO Y15...YO s/u X5...XO Y15...YO 16-BIT- 220- ADDER 16-BIT- 21 OADDER 215 S15...SO s/U X31.x16 Y31...Y.6 s/u X31...XO Y31...YO 16-BT ADDER 16-BET ADDER Cin Cin - 24 O - 25 O 245 S51...S16 235 S15...SO F.G. 5 C U.S. Patent Jul. 7, 1998 Sheet 4 of 32 5,778,241 s/u X51...XO Y31...YO 32-BIT Logic Unit - 2 OO- Cin 305 R31...RO F.G. 4 O (Prior Art) s/u U15...UO W5... WO s/u X15.XO Y15...YO 16-BIT Logic Unit 16-BIT Logic Unit -32C- Cin - 31 O- Cin s/u X31.X16 Y31...Y.6 s/u X15...XO Y15...YO 16-BIT Logic Unit 16-BIT Logic Unit U.S. Patent Jul. 7, 1998 Sheet 5 of 32 5,778.241 4O1 X51 XO 32-bit shifter X31 - 4 15- XO XO X51 '1" '1' 'O' 'O' SEL SEL 400 F.G. 5 O (Prior Art) X31 XO 32-bit L/R 1-bit Shifter (1) -- 32-bit L/R 1-bit Shifter (2) 42O 32-bit L/R 1-bit Shifter (32) Z31 ZO F.G. 5 b (Prior Art) U.S. Patent Jul. 7, 1998 Sheet 6 of 32 5,778,241 }0a19s OG~º)|– U.S. Patent Jul. 7, 1998 Sheet 9 of 32 5,778.241 TagF5? S” U.S. Patent Jul. 7, 1998 Sheet 13 of 32 5,778,241 S3CJOONO|||C|NO ZNI U.S. Patent 5,778,241 159T-WEERZOG-O!"0|- U.S. Patent Jul. 7, 1998 Sheet 15 of 32 5,778.241 lower MAC Accumulo tor Register File Upper MAC Accumulotor Register File U.S. Patent Jul. 7, 1998 Sheet 16 of 32 5,778.241 Multiply Source Operand Format 16 Bit Source Operand Format S u l l l l l l. l l l l l l 32 Bit Source Operand Format l l l ll SI Signed int SF Signed frac S Sign bit U. Unsigned int UF Unsigned frac u unsigned bit. 32-Bit Multiply Product Scaling relative to accumulator) G A. A. A. A. A. A A. A. A. A. A. A A. A. A. A. A. A. A A. A. A. A A. A. A A. A. SS s s S . l l l Six s S xS. Ex : S S S S S S S S S S u u u u u ul l l l l l l l l l l l l l l l l SIXUF S S S S S S S S S u u u u u u u u u u i u u u u u u u u u u u u u u u i u u u UIXSF s is s s s S s S S u u u u u u u u u u u u u u u u. u u u u u u u u u u u u u u u UIXUF O C o O C o O O u u u u u u u u u u u u u u u u. u u u u u u u u u u u u u u u u SFXSI is s S s s s is S S S u u u i u u u u u u u u u. u u u u u i u u u u u u ul SFXUI is S S S S S S S S i u u u i u u u u u u u u u u.u u u u u u u u u u u u u u OFXS is S S S S S S S S u u u u u u u u u u u u u, u u u u u u u u u u u u u : u u UFXI C C C O C C C C u u u u u u u li ul i u u , u, u, u, u u u u u u u u u u u u u u u u S. S S S S S S S S. u ul i u : ) u u u u u u l l l l l l l l l S S S S 3 S S S S. i u li u u u li u , u, u u u u u l l l l l l l l l l l l l l li s S S S S S S is S. l l l l l l l l l l l l u u u ul l l l l l l l l l l l l C C C C C C C & . Al l l l l l l l l l l l l l l * Product is left shifted by are bit position for 6 x 15, SFxSF multiply only.i is SI Signed int. SF Signed frac S Sign blit s Sign extend bit G Guard cit I Unsigned int UF Unsigned frac unsigned bit o 2ero extend bit A. Accum bit F.G. 14 U.S. Patent Jul. 7, 1998 Sheet 17 of 32 5,778.241 48-Bit Multiply Right Justified Product Scaling relative to accumulator) Guarded Accumulator in Upper MAC A. A. A. A. A. A. A. A. A. A. A. A. A. A. A. A. A. A s S S is is s s s s s S S. S. S S S. S S s s is is s s S S S C C.