EECS 470 Lab 3 SystemVerilog Style Guide Department of Electrical Engineering and Computer Science College of Engineering University of Michigan Friday, 24th January, 2014 (University of Michigan) Lab 3: Style Friday, 24th January, 2014 1 / 36 Overview Administrivia Verilog Style Guide Brevity Indentation and Alignment SystemVerilog Features Finite State Machines Project 2 Assignment (University of Michigan) Lab 3: Style Friday, 24th January, 2014 2 / 36 Administrivia Administrivia Homework rd I Homework 2 is due Monday, 3 February at the beginning of lecture Projects st I Project 2 is due Monday, 27 January at 9:00PM Help We are available to answer questions on anything here. Office hours can be found in the course google calendar. Due to room scheduling conflicts, office hours might in 1620 or 1695. Please check both before posting to Piazza asking where we are. (University of Michigan) Lab 3: Style Friday, 24th January, 2014 3 / 36 Verilog Style Guide Verilog Style What is good style? I Easy to read I Easy to understand I Mostly a matter of personal preference Why should I use good style? I Easier to debug I Important for group work I Mandatory in projects 1-3 (University of Michigan) Lab 3: Style Friday, 24th January, 2014 4 / 36 Verilog Style Guide Verilog Style Rules Goal: Clarity I For any problem, one solution is the clearest I We want to approximate this solution I By creating a set of rules to follow Format I We’ll look at a bad example I Then how to fix it I Derive a rule (University of Michigan) Lab 3: Style Friday, 24th January, 2014 5 / 36 Example Reformatted always_comb begin if (foo[3]) bar= 4’b1011; else if (foo[2]) bar= 4’b0100; vs. end Verilog Style Guide Brevity Brevity by Example Example always_comb begin if (foo[3] === 1’b1) begin bar[3]= 1’b1; bar[2]= 1’b0; bar[1]= 1’b1; bar[0]= 1’b1; end else if (foo[2] === 1’b1) begin bar[3]= 1’b0; bar[2]= 1’b1; bar[1]= 1’b0; bar[0]= 1’b0; end end (University of Michigan) Lab 3: Style Friday, 24th January, 2014 6 / 36 Verilog Style Guide Brevity Brevity by Example Example Example Reformatted always_comb always_comb begin begin if (foo[3] === 1’b1) if (foo[3]) bar= 4’b1011; begin else if (foo[2]) bar= 4’b0100; bar[3]= 1’b1; vs. end bar[2]= 1’b0; bar[1]= 1’b1; bar[0]= 1’b1; end else if (foo[2] === 1’b1) begin bar[3]= 1’b0; bar[2]= 1’b1; bar[1]= 1’b0; bar[0]= 1’b0; end end (University of Michigan) Lab 3: Style Friday, 24th January, 2014 6 / 36 Example Reformatted logic[5:0] shift; always_ff@(posedge clock) begin vs. if (reset) begin shift <=#1 6’b0; end else begin shift <=#1 {shift[4:0], foo}; end end Verilog Style Guide Brevity Brevity by Example Example logic[5:0] shift; always_ff@(posedge clock) begin if (reset) begin shif_reg <=#1 6’b0; end else begin shift[0] <=#1 foo; shift[1] <=#1 shift[0]; shift[2] <=#1 shift[1]; shift[3] <=#1 shift[2]; shift[4] <=#1 shift[3]; shift[5] <=#1 shift[4]; end end (University of Michigan) Lab 3: Style Friday, 24th January, 2014 7 / 36 Verilog Style Guide Brevity Brevity by Example Example Example Reformatted logic[5:0] shift; logic[5:0] shift; always_ff@(posedge clock) always_ff@(posedge clock) begin begin if (reset) vs. if (reset) begin begin shif_reg <=#1 6’b0; shift <=#1 6’b0; end else begin end else begin shift[0] <=#1 foo; shift <=#1 {shift[4:0], foo}; shift[1] <=#1 shift[0]; end shift[2] <=#1 shift[1]; end shift[3] <=#1 shift[2]; shift[4] <=#1 shift[3]; shift[5] <=#1 shift[4]; end end (University of Michigan) Lab 3: Style Friday, 24th January, 2014 7 / 36 Verilog Style Guide Brevity Brevity Rule Rule Brevity is strongly correlated with the optimal solution. Be brief, where you can. (University of Michigan) Lab 3: Style Friday, 24th January, 2014 8 / 36 Verilog Style Guide Brevity General Requirements Clarity Rules I Use meaningful names for signal; wire wire; is confusing I Comment your designs; (a ˆ b ˜ˆ c) | (&d) is unintelligible without an explanation I Conceptualize what you need to build before you start writing Verilog. A state machine diagram will be make the Verilog much easier. (University of Michigan) Lab 3: Style Friday, 24th January, 2014 9 / 36 Verilog Style Guide Indentation and Alignment Indentation Why are we interested in indentation? I Readability – easier to trace down I Clarity – easier to check what is in a given scope (University of Michigan) Lab 3: Style Friday, 24th January, 2014 10 / 36 Example Reformatted always_comb begin if (cond) begin n_state= `IDLE; vs. n_gnt= `NONE; end else begin n_state= `TO_A; n_gnt= `GNT_A; end end Verilog Style Guide Indentation and Alignment Indentation by Example Example always_comb begin if(cond) begin n_state= `IDLE; n_gnt= `NONE; end else begin n_state= `TO_A; n_gnt= `GNT_A; end end (University of Michigan) Lab 3: Style Friday, 24th January, 2014 11 / 36 Verilog Style Guide Indentation and Alignment Indentation by Example Example Example Reformatted always_comb always_comb begin begin if(cond) if (cond) begin begin n_state= `IDLE; n_state= `IDLE; n_gnt= `NONE; vs. n_gnt= `NONE; end else begin end else begin n_state= `TO_A; n_state= `TO_A; n_gnt= `GNT_A; n_gnt= `GNT_A; end end end end (University of Michigan) Lab 3: Style Friday, 24th January, 2014 11 / 36 Verilog Style Guide Indentation and Alignment Indentation Rule Rule Items within the same scope should have the same indentation. (University of Michigan) Lab 3: Style Friday, 24th January, 2014 12 / 36 Verilog Style Guide Indentation and Alignment Alignment Why are we interested in alignment? I Readability – easier to trace down I Clarity – easier to check that everything is assigned (University of Michigan) Lab 3: Style Friday, 24th January, 2014 13 / 36 Example Reformatted always_comb begin if (cond) begin n_state= `IDLE; vs. n_gnt= `NONE; end else begin n_state= `TO_A; n_gnt= `GNT_A; end end Verilog Style Guide Indentation and Alignment Alignment by Example Example always_comb begin if (cond) begin n_state= `IDLE; n_gnt= `NONE; end else begin n_state= `TO_A; n_gnt= `GNT_A; end end (University of Michigan) Lab 3: Style Friday, 24th January, 2014 14 / 36 Verilog Style Guide Indentation and Alignment Alignment by Example Example Example Reformatted always_comb always_comb begin begin if (cond) if (cond) begin begin n_state= `IDLE; n_state= `IDLE; n_gnt= `NONE; vs. n_gnt= `NONE; end else begin end else begin n_state= `TO_A; n_state= `TO_A; n_gnt= `GNT_A; n_gnt= `GNT_A; end end end end (University of Michigan) Lab 3: Style Friday, 24th January, 2014 14 / 36 Example Reformatted assign mux_out= (cond1)? (foo1& bar): (cond2)? (foo2+ cnt3): (cond3)? (foo3&~bar2):0; Verilog Style Guide Indentation and Alignment Alignment by Example Example assign mux_out= (cond1)? (foo1&bar): (cond2)? (foo2+cnt3): (cond3)? (foo3&~bar2):0; (University of Michigan) Lab 3: Style Friday, 24th January, 2014 15 / 36 Verilog Style Guide Indentation and Alignment Alignment by Example Example assign mux_out= (cond1)? (foo1&bar): (cond2)? (foo2+cnt3): (cond3)? (foo3&~bar2):0; Example Reformatted assign mux_out= (cond1)? (foo1& bar): (cond2)? (foo2+ cnt3): (cond3)? (foo3&~bar2):0; (University of Michigan) Lab 3: Style Friday, 24th January, 2014 15 / 36 Verilog Style Guide Indentation and Alignment Alignment Rule Rule Assignments should be aligned by column. Ternary statements should have the conditionals aligned, and each “if” should be on a new line. (University of Michigan) Lab 3: Style Friday, 24th January, 2014 16 / 36 Verilog Style Guide SystemVerilog Features SystemVerilog Types User-defined Types I Useful for cleaning repeated declarations, specifically bundling connections I Types can be named informatively, e.g. arch_reg_t (University of Michigan) Lab 3: Style Friday, 24th January, 2014 17 / 36 Verilog Style Guide SystemVerilog Features Structs About struct I A package of signals (wire or logic) I Basically follow C conventions I List of signal declarations I Named with _t ending I Only struct packed is synthesizable, more in lab 6 Syntax I struct I List of signals between braces ({}) I Name after braces, followed by a semicolon (;) (University of Michigan) Lab 3: Style Friday, 24th January, 2014 18 / 36 Verilog Style Guide SystemVerilog Features Structs Example typedef struct packed{ logic[7:0] a; //Structs can contain logic b; //other structs, like arch_reg_t c; //<-- this line } example_t; //named with _t Example typedef struct packed{ addr_t pc; logic valid; } prf_entry_t; Usage Example prf_entry_t [31:0] prf; assign prf[1].valid= 1’b0; (University of Michigan) Lab 3: Style Friday, 24th January, 2014 19 / 36 Verilog Style Guide SystemVerilog Features Enums About enum I List of possible values, but named instead of numbered I Good for state machine states I Can be shown in DVE instead of the associated value Syntax I enum I List of values between braces ({}) I Name after braces, followed by a semicolor (;) (University of Michigan) Lab 3: Style Friday, 24th January, 2014 20 / 36 Verilog Style Guide SystemVerilog Features Enums Example typedef enum logic[3:0]{ IDLE, //=0, by default GNT[0:7], //Expands to GNT0=1,...GNT7=8 RESET //=9 } arb_state; Example typedef enum logic[1:0]{ ADD= 2’b00, //The value associated with MULT= 2’b10, //a particular name can be NOT= 2’b11, //assigned explicitly. AND= 2’b01 } opcode; Usage Example arb_state state, n_state; assign n_arb_state= IDLE; (University of Michigan) Lab 3: Style Friday, 24th January, 2014 21 / 36 Verilog Style Guide SystemVerilog Features Enums DVE Example (University of Michigan) Lab 3: Style Friday, 24th January, 2014 22 / 36 Verilog Style Guide SystemVerilog Features Typedef About typedef