İSTANBUL TECHNICAL UNIVERSITY ELECTRICAL - ELECTRONICS ENGINEERING FACULTY Design And Verification Of An 16-Bit Floating Point Alu, Using Universal Verification Method BSc Thesis by Yasin Fırat Kula 040110020 Department: Electronics and Communication Engineering Programme: Electronics and Communication Engineering Supervisor: Assoc. Prof. Dr. Sıddıka Berna ÖRS YALÇIN MAY 2016 PREFACE First of all, thanks to all of my respectable college teachers who pass on their great knowledge throughout BSc program ,with a special thanks to my teacher and project advisor Assoc. Prof. Dr. Sıddıka Berna Örs Yalçın for her invaluable information and support in the course of the project. Also, I would like to thank Güler ÇOKTAŞ for her help and guidance during the process of the thesis. Lastly, I present my eternal gratitude to my family, who've been always been with me from the beginning to the present, and bringing me where I am now. MAY 2016 Yasin Fırat KULA ii TABLE OF CONTENTS LIST OF ABBREVATIONS......................................................................................v LIST OF TABLES.....................................................................................................vi LIST OF FIGURES..................................................................................................vii ÖZET........................................................................................................................viii SUMMARY................................................................................................................ix 1. INTRODUCTION.................................................................................................1 2. BACKGROUND...................................................................................................3 2.1.Floating Point Numbers.................................................................................3 2.1.1. General Information..............................................................................3 2.1.2. IEEE-754 Half Precision Floating Point System..................................4 2.2.Floating Point ALU.........................................................................................4 2.3.Verification......................................................................................................5 2.4.Universal Verification Methodology (UVM)................................................6 3. DESING AND VERIFICATION TOOLS..........................................................7 3.1.Xilinx ISE Design Suite..................................................................................7 3.2.SVEditor..........................................................................................................8 3.3.QuestaSim........................................................................................................9 4. HARDWARE DESIGN......................................................................................11 4.1.Overview........................................................................................................11 4.2.Floating Point Division Module...................................................................11 4.2.1. Top Module.........................................................................................11 4.2.2. Unpacker.............................................................................................14 4.2.3. Sign Calculator....................................................................................14 4.2.4. Exponent Subtractor............................................................................15 4.2.5. Mantissa Divider.................................................................................16 4.2.6. Normalizer..........................................................................................17 4.2.7. Packer..................................................................................................18 4.3.Behavioral Simulation..................................................................................19 4.3.1. Basic Simulation.................................................................................19 4.3.2. Pipeline Testing..................................................................................20 iii 5. FLOATING POINT DIVISION MODULE VERIFICATION.....................22 5.1.General Structure.........................................................................................22 5.2.UVM Top Module.........................................................................................23 5.3.Interface.........................................................................................................24 5.4.UVM Components........................................................................................25 5.4.1. Test Module and Environment............................................................25 5.4.2. Agent...................................................................................................26 5.4.3. Monitor...............................................................................................28 5.4.4. Sequencer and Sequences...................................................................29 5.4.5. Driver..................................................................................................30 5.4.6. Subscriber...........................................................................................31 5.4.7. Scoreboard..........................................................................................31 5.4.7.1.SystemVerilog Direct Programming Interface (DPI)...................32 5.4.7.2.MATLAB Predictor Module.........................................................32 6. RUNNING THE UVM TESTBENCH WITH QUESTASIM.........................34 7. CONCLUSION...................................................................................................35 REFERENCES..........................................................................................................36 APPENDICES...........................................................................................................39 RESUME..................................................................................................................TB iv LIST OF ABBREVIATONS UVM : Universal Verification Methodology ALU : Arithmetic Logic Unit IVB : Incisive Verification Builder IEEE : Institute of Electrical and Electronics Engineers OVM : Open Verification Methodology AVM : Advanced Verification Methodology VMM : Verification Methodology Manual HDL : Hardware Description Language FPGA : Field Programmable Gate Array IDE : Integrate Development Environment SoC : System on Chip ASIC : Application Specific Integrated Circuit RTL : Register Transfer Level DUT : Design Under Test TLM : Transaction Level Modeling DPI : Direct Programming Interface v LIST OF TABLES Table 2.1 : Available formats of IEEE-754 number system........................................3 Table 4.1 : List of bit codes for each exception in division module..........................12 Table 5.1 : List of port types in TLM........................................................................27 vi LIST OF FIGURES Figure 2.1 : Bit arrangement of "binary16" system.....................................................4 Figure 3.1 : A screenshot of HDL design environment of ISE ...................................7 Figure 3.2 : A simulation screen from ISE integrated ISIM simulator........................8 Figure 3.3 : An RTL schematic in display at ISE........................................................8 Figure 3.4 : SVEditor design environment..................................................................9 Figure 3.5 : A screenshot from QuestaSim simulation environment.........................10 Figure 4.1 : Top layer RTL schematic of top module...............................................13 Figure 4.2 : The circuit schematic of division module..............................................13 Figure 4.3 : Top layer RTL schematic of unpacker...................................................14 Figure 4.4 : RTL schematic of sign calculator...........................................................15 Figure 4.5 : Top layer RTL schematic of exponent subtractor..................................15 Figure 4.6 : Top layer RTL schematic of normalizer................................................18 Figure 4.7 : Top layer RTL schematic of packer.......................................................19 Figure 4.8 : Waveforms of division module's basic simulation.................................20 Figure 4.9 : Waveforms of division module's pipelining simulation.........................21 Figure 5.1 : A typical UVM top module....................................................................22 Figure 5.2 : Interaction of top module elements........................................................23 Figure 5.3 : Interface's connection with other components.......................................24 Figure 5.4 : List of UVM phases...............................................................................25 Figure 5.5 : A showcase of top layer elements..........................................................26 Figure 5.6 : An active agent.......................................................................................27 Figure 5.7 : A picture of TLM analysis ports and exports in analysis layer..............28 Figure 5.8 : Image of the links between sequencer, sequence and sequence item....29 Figure 5.9 : Sequencer-Driver-DUT transaction.......................................................30