IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL.NO. ED-29, 5, MAY 1982 821 and J(n) are functions of position, 0 < X < L. The coeffi- cell,” Solid-State Electron., vol. 10, p. 765, 1967. T.i,, [4] J. L. Boone and T. P. Van Doren, “Solar-cell design based on a dis- cients J(m)are derivatives of the intrinsic ‘diode characteristic tributed diode analysis,” IEEE Trans. Electron Devices, vol. ED-25, at Y=V, (8). p. 767, 1978. [5] H. J. Hovel, “Solar cells,” in Semiconductors andSemimetals, vol. REFERENCES 11, R. K. Willadson and A.C. Beer, Eds. New York: Academic Press, 1975. [ 11 M. Wolf, “Limitations and possibilities for improvement of photo- [6] R. N. Hall, “Silicon photovoltaic cells,” Solid-Sfate Electron., vol. voltaic solar energy converters,”Proc. IRE, vol. 48, p. 1246, 1960. 24, p. 595, 1981. [ 21 J. J. Wysocki, “The effect of series resistance on photovoltaic solar [7] M. Wolf and H. Rauschenbach, “Series resistance effects on solar energy conversion,” RCA Rev., vol. 22, p. 57, 1961. cell measurements,” Advanced Energy Conversion, vol. 3, p. 455, [3] R. J. Handy, “Theoretical analysis of the series resistance of a solar 1963. An Area-Variable MOS Varicap and Its Application in Programmable TAP Weighting of CCD Transversal Filters A. B. BHATTACHARYYA AND HANS WALLINGA Abstract-Anew three-terminal MOS varicap is proposedwhere I. INTRODUCTION the terminal capacitors are made voltage variable not by the modula- tion of depletion width but bychanging the area of inversion under the OLTAGE ‘VARIABLE CAPACITORS or varicaps have gate. An MOS capacitor realized on silicon with an impurity gradient V found a wide range of applications such as voltage con- along the surface provides the control on the area of inversion because trolled oscillators, tunableintegrated circuits, FM deviators the gate threshold voltage is determined by thedoping concentration at [l], and specific tuningelements [2], [3],etc. Generally, the surface. The inhomogeneous doping along the surface is implemented making such capacitors are two-terminal elements realized with a pn use of the lateral diffusion from a doped oxide surface. Fabrication junction or MOS structure and their capacitance variation with details of the capacitor compatible withn-channel silicon gate tech- voltage dependson the principle thatthe depletion width nology are presented. The C- V relationship for the terminal capacitors either at the p-n junction or at the semiconductor-insulatorin- is simulated by a piecewise model and agreement with measured results terface in the deep depletion mode can be controlled electric- is shown. ally. Since the capacitance is directly proportional to the area The Area-Variable MOS Varicap (AVMOSV) is used in implementing an electrically programmable CCD filter with variable TAP weighting. and inversely proportional tothe depletion width, conven- Computer simulationshows considerable promise of area-variable tional capacitances with a given area decrease with increasing capacitors in TAP weight control and transversal filter realization. Pre- voltage. There are, however, specific needs where more func- liminary performance characteristics of a programmable CCD filter are tional flexibility is required such as in a high-frequency switch- presented. ing application when a three-terminal structure is suitable [4]. On-chip MOS varicaps have been used recently for introduc- ing a compact circuit for programming the TAP weights of a Manuscript received May 8, 198l;revised October 7, 1981. Financial CCD filterelectronically [5], [6]. In suchimplementations, support for this paper was made possible by the Department of Elec- tronics, Indian Institute of Technology, New Delhi, India, the Govern- the sense gates of a CCD are loaded by varicaps and a parallel ment of India, and The Twente University of Technology, Enschede, sense capacitor.The part of the CCD image-signal charge The Netherlands. through the sense capacitor depends on the ratio of the vari- A. B. Bhattacharyya is with the Centre for Applied Research in Elec- tronics, Indian Institute of Technology,Hauz Khas, New Delhi, 110 016 able MOS capacitor value andfixed sense capacitor. This India. part or fraction is controlled or programmed by voltage. The H. Wallinga was with the Solid State Electronics Group, Department advantage of capacitive weighting is the low power dissipation of Electrical Engineering, The Twente University of Technology, 7500 AE Enschede, PB 217, The Netherlands. He is now on a visiting assign- and smaller chip area compared to the structures where a com- ment at General Electric Company, Schenectady, NY 12301. bination of a floating sense gate and a buffer circuit performs 0018-9383/82/0500-0827$00.75 0 1982 IEEE 828 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. ED-29, NO. 5, MAY 1982 depends on the doping concentration at the interface; it in- creases with doping. Thusfor the MOS capacitorextending over the region A to A’, the gate voltage required for surface inversion at 0 and 0’ is larger than that required at A and A‘ since concentration of impurity decreases from 0 to A and Contact 0’ to A‘. In other words, if the gate bias is swept over the diffusion ~~e?on 1 threshold voltage range covering the doping at A/A’ and O/O’, the inversion layer will spread fromA to 0 and A’ to 0’. Thus the area under inversion is controlled electronically. For the p-substrate under consideration, theinversion charge is made of electrons. An electrical contact with the inversion 8 layer is established through n+-diffusedregion. The above structure can be visualized as a three-terminal ca- pacitor with a single control terminal. The configuration leads Fig. 1. The proposed area-variable MOS varicap structure on inhomo- geneously doped surface. 1) The thick doped oxide serves as diffu- to two capacitive components: sion source. 2) Inset (a) shows the impurity profilealong the sur- 1) The oxide capacitor Ci,z between the gate terminal 0 face. 3) Inset (b) shows thethreshold voltagevariation along the and the inversion layer accessed through In the illustration surface. 0. shown in Fig. 1, the capacitance C1, is determined by the in- version length A2 (A’Z’)and the gate width W,i.e., the area a charge-to-voltage conversion and variable TAP weighting is and the oxide thickness. With increasing gate voltage the area obtained by means of an MOS transistor acting as an analog of inversion and hence the capacitance C1, increases. multiplier [7], [12] or variable conductance MOST devices 2) C1, is the capacitor between the controlling gate termi- [8] . In the varicap-based implementations realized thus far, nal @ and the substrate 0.In the given diagram the region the sensed charge was only 10 percent of the signal charge in under Z(Z’)to O(0’) is still uninverted because the applied a CCD and, therefore, the insertion loss was high [SI . gate voltage is less for inverting this region with higher doping. In this paper, a new three-terminal MOS varicap is proposed The uninverted region will contribute a capacitance between where the terminal capacitors are made voltage dependent by gate and substrate which is composed of a series combination effecting variationsin the effectivearea ratherthan in the of oxide capacitance and depletion capacitance. The contribu- depletionlayer width. An MOS capacitoron an inhomoge- tion of capacitor due to the part 00’ is negligible due to thick neously doped silicon surface provides the possibility of real- oxide. izing the voltage controlled area of the inversion layer since In the previously mentioned structure as the area under in- the threshold voltage has adependence on doping. Such an version increases, that in anoninverted condition decreases. area-variable three-terminal capacitor, in a very compact and Thus with an increase in the gate voltage at a,C1,2 increases elegant manner, integrates the basic functionalrequirement and C1, decreases. of programmable capacitive TAP weighting required for CCD It may be noted that unlike conventional MOS or p-n junc- transversal filtering. It also offers significant advantages over tion varactors, the voltage dependence on the capacitor is not schemes belonging to this category in terms of the economy due to modulation of the depletion layer width but due to the of the silicon area, the capability of relative TAP weight varia- variation in the area determining the capacitance. tion, and the insensitivity to parasitics inherent in such con- figurations. 111. FABRICATION Inthe following sections,the basicphysics ofthe area- An AVMOSV was fabricated using n-channel Si-gate tech- variable MOS varicap, its fabrication, computer simulation for nology. As shown in Fig. 1, the thick doped oxide defines the the characteristics, and its application to the realization C-V source for lateral andvertical diffusion. Under the doped oxide of programmable CCD transversal filtering are presented. 00’, at the surface (y= 0), the surface concentration C, is the highest. The essential components of the capacitor, defining 11. PRINCIPLEOF AN AREA-VARIABLEMOS VARICAP(AVMOSV) the masks, are the thick oxide for lateral diffusion n+-contact diffusions, thin gate oxide, and the top poly-Si gate electrode. The principle of operation of an AVMOSV is illustrated in Fig. 2 gives the processsequence based on CVD techniques Fig. 1, where along the surface of p-type silicon an impurity used for doping and poly-Si realization. Some of the relevant gradient is realized along OA and O’A’. In a practicalimple- technological details are outlined in the diagram. mentation this is achieved by carrying out diffusion from the doped oxide source between 0 and 0’ which results in a ver- IV. COMPUTERSIMULATION AND EXPERIMENTALRESULTS ticaldiffused profile along they-direction and a horizontal impurity gradientalong thex-direction due to lateraldif- Thedoped boron oxide provides the impurity gradient of fusion. Subsequently, an MOS capacitor is fabricated on the boron impurities in p-substrate.