Hardware Modules for Safe Integer and Floating-Point Arithmetic A Thesis submitted to the Graduate School Of The University of Cincinnati In partial fulfillment of the requirements for the degree of Master of Science in the Department of Electrical Engineering and Computing Systems of the College of Engineering and Applied Science 2013 by Amrita Ratan BS, North Dakota State University, 2010 Committee Chair: Dr. Carla Purdy i ABSTRACT Integer and floating-point data types are widely used to represent numerical data in computer arithmetic. Since the range of values representable in a computer are limited, arithmetic operations on these data types can lead to overflows and underflows. More often than not, silent overflows and underflows are permitted by software and even though hardware records these errors, it may not be designed to handle them. These errors can be a threat to security and can reduce the reliability of software. In this work we present a hardware design for an Arithmetic and Logic Unit (ALU), and for a Floating- Point Unit (FPU). The ALU and FPU record and gracefully handle overflows and underflows. They have three modes of operation and handle overflows and underflows differently in each mode. The mode may be selected based on the requirement of the application. The designs have been implemented in Verilog and have been verified on the Altera DE2-115 Board. This method can be modified for use in any hardware design. ii iii Table of Contents 1. OVERVIEW ......................................................................................................................................... 1 2. BACKGROUND ................................................................................................................................... 3 2.1 Software Reliability ......................................................................................................................... 3 2.2 Integer Exceptions........................................................................................................................... 4 2.3 Floating-Point Exceptions ............................................................................................................... 7 2.4 Aim of the Thesis ............................................................................................................................. 9 3. APPROACH ...................................................................................................................................... 10 3.1. Structure of This Chapter ............................................................................................................. 10 3.2 ALU and FPU Design Outline ......................................................................................................... 10 3.3 ALU for Handling Integer Overflows and Underflows ................................................................... 15 3.3.1 Addition and Subtraction ........................................................................................................... 15 3.3.2 Multiplication ............................................................................................................................. 16 3.3.3 Division ....................................................................................................................................... 17 3.4 FPU Design for Handling Floating-Point Overflows, Underflows, Invalid and Divide-by-Zero Exceptions ........................................................................................................................................... 20 3.4.1 Addition and Subtraction ........................................................................................................... 22 3.4.2 Multiplication ............................................................................................................................. 26 3.4.3 Division ....................................................................................................................................... 28 3.5 ALU and FPU Implementation on Altera’s DE2-115 Board ........................................................... 31 4. RESULTS ........................................................................................................................................... 34 4.1 Results of Arithmetic Operations Performed by the ALU ............................................................. 34 4.1.1 Addition ...................................................................................................................................... 34 4.1.2 Subtraction ................................................................................................................................. 38 4.1.3 Multiplication ............................................................................................................................. 42 4.1.4 Division ....................................................................................................................................... 44 4.2 Results of Arithmetic Operations Performed by the FPU ............................................................. 47 4.2.1 Addition ...................................................................................................................................... 47 4.2.2 Subtraction ................................................................................................................................. 54 4.2.3 Multiplication ............................................................................................................................. 61 4.2.4 Division ....................................................................................................................................... 67 iv 5. CONCLUSIONS AND FUTURE WORK................................................................................................ 74 REFERENCES ........................................................................................................................................ 75 v List of Figures Figure 3.1: Flowchart describing the three modes of ALU/FPU operation................................................. 13 Figure 3.2: Modular design of the ALU ....................................................................................................... 14 Figure 3.3: Modular design of the FPU ....................................................................................................... 14 Figure 3.4: Verilog code implementing partial product generation from Booth algorithm ....................... 17 Figure 3.5: Verilog implementation of first shift-add/subtract cycle in nonrestoring division algorithm .. 19 Figure 3.6: The sign, exponent and significand fields in single precision and double precision formats ... 21 Figure 3.7: Monitoring significand overflow and corresponding exponent overflow during addition ...... 23 Figure 3.8: Flowchart describing basic process for recording overflow, underflow and invalid operation in addition and subtraction in FPU ................................................................................................................. 25 Figure 3.9: Flowchart describing process for recording overflow, underflow and invalid operation in multiplication in FPU ................................................................................................................................... 28 Figure 3.10: Logic for determining overflow during floating-point division ............................................... 30 Figure 3.11: Flowchart describing process for recording overflow, underflow and invalid operation in division in FPU ............................................................................................................................................. 32 vi List of Tables Table 3.1: Booth multiplier partial product generation and multiplier recoding ....................................... 17 Table 3.2: Base 2 representation of floating-point data in single precision format ................................... 22 Table 4.1: Maximum and minimum values representable by operands ‘A’ and ‘B’ and result ‘Sum’ ........ 35 Table 4.2: Results of integer number addition with ALU set in each one of its three modes .................... 38 Table 4.3: Maximum and minimum values representable by operands ‘A’ and ‘B’ and result ‘Difference’ .................................................................................................................................................................... 39 Table 4.4: Results of integer number subtraction with ALU set in each one of its three modes ............... 42 Table 4.5: Maximum and minimum values representable by operands ‘A’ and ‘B’ and result ‘Product’ .. 43 Table 4.6: Results of integer number multiplication with ALU set in its first mode ................................... 44 Table 4.7: Maximum and minimum values representable by operands ‘A’ and ‘B’ and result ‘Remainder’ and ‘Quotient’ ............................................................................................................................................. 46 Table 4.8: Results of integer number division with ALU set in each one of its three modes ..................... 47 Table 4.9: Maximum and minimum values represented by variables A, B and Sum ................................. 49 Table 4.10: Results of floating-point addition with FPU set in each one of its three modes ..................... 54 Table 4.11: Maximum and minimum values representable