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Copyright© Intel Corporation 2002 2 Intel® 80331 I/O Processor Design Guide Contents Contents 1 Introduction..................................................................................................................................11 1.1 About This Document .........................................................................................................11 1.1.1 Terminology and Definitions ..................................................................................12 1.1.2 Other Relevant Documents ...................................................................................14 1.2 About the Intel® 80331 I/O Processor.................................................................................15 2 Package Information ...................................................................................................................17 2.1 Power Plane Layout............................................................................................................21 2.2 Intel® 80331 I/O Processor Applications.............................................................................22 3Terminations................................................................................................................................23 3.1 Analog Filters......................................................................................................................27 3.1.1 VCCPLL Pin Requirements......................................................................................27 3.2 DDR Resistor Compensation..............................................................................................28 3.3 DDR Driver Compensation .................................................................................................29 4 Routing Guidelines......................................................................................................................31 4.1 General Routing Guidelines................................................................................................31 4.2 Crosstalk.............................................................................................................................32 4.3 EMI Considerations ............................................................................................................34 4.4 Power Distribution and Decoupling.....................................................................................34 4.4.1 Decoupling.............................................................................................................34 4.5 Trace Impedance................................................................................................................36 5 Board Layout Guidelines ............................................................................................................37 5.1 Motherboard Stack Up Information.....................................................................................37 5.2 Adapter Card Stackup ........................................................................................................39 6 PCI-X Layout Guidelines.............................................................................................................41 6.1 Interrupt Routing and IDSEL Lines .....................................................................................41 6.1.1 PCI Arbitration .......................................................................................................42 6.1.2 PCI Resistor Compensation ..................................................................................42 6.2 PCI General Layout Guidelines ..........................................................................................43 6.3 PCI-X Topology Layout Guidelines.....................................................................................43 6.4 Intel® 80331 I/O Processor PCI/X Layout Analysis ............................................................44 6.4.1 PCI Clock Layout Guidelines .................................................................................45 6.4.2 Single-Slot at 133 MHz ..........................................................................................48 6.4.3 Embedded PCI-X 133 MHz ...................................................................................49 6.4.4 Embedded PCI-X 133 MHz Alternate Topology ....................................................50 6.4.5 Combination of PCI-X 133 MHz Slot and Embedded Topology ............................51 6.4.6 Combination PCI-X 133 MHz Slot and Embedded Topology 2 .............................52 6.4.7 PCI-X 100 MHz Slot Topology...............................................................................53 6.4.8 PCI-X 100 MHz Embedded Topology....................................................................54 6.4.9 PCI-X 100 MHz Slot and Embedded Topology......................................................55 6.4.10 PCI-X 100 MHz Slot and Embedded Topology 2...................................................56 6.4.11 PCI-X 66 MHz Slot Topology.................................................................................57 6.4.12 PCI-X 66 MHz Embedded Topology......................................................................58 6.4.13 PCI-X 66 MHz Mixed Mode Topology....................................................................59 3 Intel® 80331 I/O Processor Design Guide Contents 6.4.14 PCI 66 MHz Slot Topology .................................................................................... 60 6.4.15 PCI 66 MHz Embedded Topology .........................................................................61 6.4.16 PCI 66 MHz Mixed Mode Topology ....................................................................... 62 6.4.17 PCI 33 MHz Slot Topology .................................................................................... 63 6.4.18 PCI 33 MHz Embedded Mode Topology ............................................................... 64 6.4.19 PCI 33 MHz Mixed Topology ................................................................................. 65 7 Memory Controller.......................................................................................................................67 7.1 DDR Bias Voltages.............................................................................................................67 7.2 Intel® 80331 I/O Processor DDR Overview ........................................................................ 68 7.3 DDR 333 Signal Integrity Simulation Conditions ................................................................ 69 7.3.1 DDR 333 Stackup Example ................................................................................... 70 7.4 DDR Layout Guidelines ...................................................................................................... 72 7.4.1 Source Synchronous Signal Group ....................................................................... 72 7.4.1.1 Routing Requirements ........................................................................... 73 7.4.2