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Copyright © Intel Corporation, 1997 *Third-party brands and names are the property of their respective owners. ii May, 1998 272483-002 i960® Jx Microprocessor Developer’s Manual CHAPTER 1 INTRODUCTION 1.1 Product Features........................................................................................................... 1-4 1.1.1 Instruction Cache .................................................................................................... 1-4 1.1.2 Data Cache ............................................................................................................. 1-4 1.1.3 On-chip (Internal) Data RAM ................................................................................... 1-4 1.1.4 Local Register Cache .............................................................................................. 1-5 1.1.5 Interrupt Controller .................................................................................................. 1-5 1.1.6 Timer Support .......................................................................................................... 1-6 1.1.7 Memory-Mapped Control Registers (MMR) ............................................................. 1-6 1.1.8 External Bus ............................................................................................................ 1-6 1.1.9 Complete Fault Handling and Debug Capabilities ................................................... 1-7 1.2 ABOUT THIS MANUAL................................................................................................. 1-7 1.3 NOTATION AND TERMINOLOGY................................................................................ 1-8 1.3.1 Reserved and Preserved ......................................................................................... 1-8 1.3.2 Specifying Bit and Signal Values ............................................................................. 1-9 1.3.3 Representing Numbers ........................................................................................... 1-9 1.3.4 Register Names ....................................................................................................... 1-9 1.4 Related Documents..................................................................................................... 1-10 CHAPTER 2 DATA TYPES AND MEMORY ADDRESSING MODES 2.1 DATA TYPES................................................................................................................ 2-1 2.1.1 Integers ................................................................................................................... 2-2 2.1.2 Ordinals ................................................................................................................... 2-2 2.1.3 Bits and Bit Fields .................................................................................................... 2-3 2.1.4 Triple- and Quad-Words .......................................................................................... 2-3 2.1.5 Register Data Alignment ......................................................................................... 2-3 2.1.6 Literals ..................................................................................................................... 2-4 2.2 BIT AND BYTE ORDERING IN MEMORY.................................................................... 2-4 2.2.1 Bit Ordering ............................................................................................................. 2-4 2.2.2 Byte Ordering .......................................................................................................... 2-4 2.3 MEMORY ADDRESSING MODES ............................................................................... 2-6 2.3.1 Absolute .................................................................................................................. 2-7 2.3.2 Register Indirect ...................................................................................................... 2-7 2.3.3 Index with Displacement ......................................................................................... 2-8 2.3.4 IP with Displacement ............................................................................................... 2-8 2.3.5 Addressing Mode Examples .................................................................................... 2-8 iii CHAPTER 3 PROGRAMMING ENVIRONMENT 3.1 OVERVIEW ................................................................................................................... 3-1 3.2 REGISTERS AND LITERALS AS INSTRUCTION OPERANDS................................... 3-1 3.2.1 Global Registers ...................................................................................................... 3-2 3.2.2 Local Registers ........................................................................................................ 3-3 3.2.3 Register Scoreboarding ........................................................................................... 3-4 3.2.4 Literals ..................................................................................................................... 3-4 3.2.5 Register and Literal Addressing and Alignment ....................................................... 3-4 3.3 MEMORY-MAPPED CONTROL REGISTERS.............................................................. 3-6 3.3.1 Memory-Mapped Registers (MMR) ......................................................................... 3-6 3.3.1.1 Restrictions on Instructions that Access Memory-Mapped Registers .............. 3-6 3.3.1.2 Access Faults ................................................................................................... 3-7 3.4 ARCHITECTURALLY DEFINED DATA STRUCTURES ............................................. 3-11 3.5 MEMORY ADDRESS SPACE..................................................................................... 3-13 3.5.1 Memory Requirements .......................................................................................... 3-14 3.5.2 Data and Instruction Alignment in the Address Space .......................................... 3-15 3.5.3 Byte, Word and Bit Addressing .............................................................................. 3-15 3.5.4 Internal Data RAM ................................................................................................. 3-16 3.5.5 Instruction Cache ................................................................................................... 3-16 3.5.6 Data Cache ............................................................................................................ 3-17 3.6 LOCAL REGISTER CACHE........................................................................................ 3-17 3.7 PROCESSOR-STATE REGISTERS........................................................................... 3-17 3.7.1 Instruction Pointer (IP) Register ............................................................................ 3-17 3.7.2 Arithmetic Controls (AC) Register .......................................................................... 3-18 3.7.2.1 Initializing and Modifying the AC Register ...................................................... 3-18 3.7.2.2 Condition Code (AC.cc) .................................................................................. 3-19 3.7.3 Process Controls (PC) Register ............................................................................. 3-21 3.7.3.1 Initializing and Modifying the PC Register ...................................................... 3-22 3.7.4 Trace Controls (TC) Register ................................................................................. 3-23 3.8 USER-SUPERVISOR PROTECTION MODEL ........................................................... 3-23 3.8.1 Supervisor Mode Resources ................................................................................