Lecture 10: Sequential Elements (Latches and Flip Flops) Mark McDermott Electrical and Computer Engineering The University of Texas at Austin 10/2/18 VLSI-1 Class Notes Sequencing § Combinational logic (CL) – output depends on current inputs § Sequential logic – output depends on current and previous inputs – Requires separating previous, current, future – Called state or tokens – Ex: FSM, pipeline clk clk clk clk in out CL CL CL Finite State Machine Pipeline 10/2/18 VLSI-1 Class Notes Page 2 Sequencing (cont) § If tokens moved through pipeline at constant speed, no sequencing elements would be necessary § Ex: fiber-optic cable – Light pulses (tokens) are sent down cable – Next pulse sent before first reaches end of cable – No need for hardware to separate pulses – But dispersion sets min time between pulses § This is called wave pipelining in circuits § In most circuits, dispersion is high – Delay fast tokens so they don’t catch slow ones. 10/2/18 VLSI-1 Class Notes Page 3 Sequencing Overhead § Use flip-flops to delay fast tokens so they move through exactly one stage each cycle § Inevitably adds some delay to the slow tokens § Makes circuit slower than just the logic delay – Called sequencing overhead § Some people call this clocking overhead – But it applies to asynchronous circuits too – Inevitable side effect of maintaining sequence 10/2/18 VLSI-1 Class Notes Page 4 Basic LATCH Operation Dout Dout Din Din clock clock Transparent-low Transparent-high transparent opaque transparent opaque clock clock Din Din Tdq Tdq Dout Dout Tsu Thld Tsu Thld 10/2/18 VLSI-1 Class Notes Page 5 Building a Flip-Flop with Two Latches Master Slave Dout Din clock Transparent Low Transparent High 10/2/18 VLSI-1 Class Notes Page 6 Difference between a Latch and a Flip-Flop Latch: Level sensitive Flip-flop: Edge triggered a.k.a. transparent latch, D latch a.k.a. master-slave flip-flop, D flip- flop, D register, FLOP clk clk D Q D Q Flop Latch clk D Q (latch) Q (flop) 10/2/18 VLSI-1 Class Notes Page 7 Static Latch Design • Static latches are essential for DSM applications § Tristate feedback f + Static X D Q – Backdriving risk f – Susceptible to noise on f D input f f § Buffered input X D Q + Fixes diffusion input f + Noninverting f f 10/2/18 VLSI-1 Class Notes Page 8 Static Latch Design (cont.) § Buffered output + No back driving § Widely used in standard cells f Q + Very robust (most important) X D - Rather large - f Rather slow (1.5 – 2 FO4 delays) f - High clock loading f 10/2/18 VLSI-1 Class Notes Page 9 Static Latch Design (cont.) § Datapath latch f Q + Smaller, faster - un-buffered input -> okay for datapaths X D f f f LD / STA / LD File - ALU 0 ALU 1 Arith Arith Flags Bypass Cache Integer Register Integer AGEN 10/2/18 VLSI-1 Class Notes Page 10 AMD K5: Datapath 10/2/18 VLSI-1 Class Notes Page 11 Flip-Flop Designs § Flip-flop is built as pair of back-to-back latches f f X D Q f f f f Q X D Q f f f f f f 10/2/18 VLSI-1 Class Notes Page 12 Clock Enable § Clock Enable: ignore clock when en = 0 – Mux: increases latch D-Q delay – Clock Gating: increase enable setup time, skew Symbol Multiplexer Design Clock Gating Design f en f f D 1 D Q Q D Q Latch 0 Latch Latch en en f en f f D 1 Q 0 Flop D Q D Q Flop en Flop en 10/2/18 VLSI-1 Class Notes Page 13 Reset § Force output low when reset asserted § Synchronous vs. asynchronous f f Symbol D Q D Q Flop Latch reset reset SynchronousReset f Q f f Q reset reset Q D D f f f f f f f f f AsynchronousReset Q Q f f f reset reset D f D f f f f f reset reset f f f 10/2/18 VLSI-1 Class Notes Page 14 Set / Reset § Set forces output high when enabled § Flip-flop with asynchronous set and reset f f reset set Q D f f f f set reset f f 10/2/18 VLSI-1 Class Notes Page 15 Sequencing Methods Tc Flip-Flops clk § Flip-flops clk clk Combinational Logic Flop Flop 2-Phase Transparent Latches f1 tnonoverlap tnonoverlap Tc/2 f § 2-Phase Latches 2 f1 f2 f1 Combinational Combinational Latch Logic Latch Logic Latch Half-Cycle 1 Half-Cycle 1 Pulsed Latches fp tpw f f § Pulsed Latches p p Combinational Logic Latch Latch 10/2/18 VLSI-1 Class Notes Page 16 Timing Diagrams Contamination and A tpd Combinational A Y Propagation Delays Logic Y tcd Logic Propagation Delay tpd Logic Contamination Delay tcd clk clk tsetup thold Latch/Flop Clk-Q Prop Delay tpcq D Q D Latch/Flop Clk-Q Cont. Delay Flop tccq tpcq Latch D-Q Prop Delay tpdq Q tccq Latch D-Q Cont. Delay tcdq Latch/Flop Setup Time clk t t tsetup clk setup hold t tpcq Latch/Flop Hold Time ccq thold D D Q tpdq Latch tcdq Q 10/2/18 VLSI-1 Class Notes Page 17 Master-Slave Flip-Flop Illustration of delays I2 T 2 I3 I5 T 4 I6 Q Q M D I1 T 1 I4 T 3 CLK tsetup = tpcq = thold ≥ © Digital Integrated Circuits2nd 10/2/18 VLSI-1 Class Notes Page 18 Max-Delay: Flip-Flops Tc ≥ tpd+ (tsetup + tpcq) sequencing overhead clk clk Q1 D2 F1 Combinational Logic F2 Tc t clk setup tpcq Q1 tpd D2 10/2/18 VLSI-1 Class Notes Page 20 Max Delay: 2-Phase Latches Tc ≥ tpd1 + tpd2 + tpdq1+ tpdq2 sequencing overhead f f f 1 2 1 D1 Q1 Combinational D2 Q2 Combinational D3 Q3 L1 Logic 1 L2 Logic 2 L3 f 1 f 2 Tc D1 tpdq1 Q1 tpd1 D2 tpdq2 Q2 tpd2 D3 10/2/18 VLSI-1 Class Notes Page 21 Max Delay: Pulsed Latches tpd + max(tpdq, tpcq + tsetup - tpw ) ≤ Tc sequencing overhead fp fp D1 Q1 D2 Q2 L1 Combinational Logic L2 Tc D1 tpdq (a) tpw > tsetup Q1 tpd D2 fp tpcq Tc tpw Q1 tpd tsetup (b) tpw < tsetup D2 10/2/18 VLSI-1 Class Notes Page 22 Min-Delay: Flip-Flops clk Q1 F1 CL ttcd ³-hold tccq clk D2 F2 clk t Q1 tccq cd D2 thold 10/2/18 VLSI-1 Class Notes Page 23 Min-Delay: 2-Phase Latches f1 ttcd1, cd 2³ t hold -- tccq tnonoverlap Q1 L1 CL f 2 Hold time reduced by D2 non-overlap L2 tnonoverlap f Paradox: hold applies 1 twice each cycle, vs. only tccq f2 once for flops. Q1 tcd But a flop is made of two D2 t latches! hold 10/2/18 VLSI-1 Class Notes Page 24 Min-Delay: Pulsed Latches f p Q1 tt³- tt+ L1 CL cd hold ccq pw f p Hold time increased by pulse width D2 L2 f p tpw thold Q1 tccq tcd D2 10/2/18 VLSI-1 Class Notes Page 25 Time Borrowing § In a flop-based system: – Data launches on one rising edge – Must setup before next rising edge – If it arrives late, system fails – If it arrives early, time is wasted – Flops have hard edges § In a latch-based system – Data can pass through latch while transparent – Long cycle of logic can borrow time into next – As long as each loop completes in one cycle 10/2/18 VLSI-1 Class Notes Page 26 Time Borrowing Example f1 ϕ1 Delayed f2 f1 f2 f1 Combinational (a) Combinational Logic Latch Latch Logic Latch Borrowing time across Borrowing time across half-cycle boundary pipeline stage boundary f1 f2 Combinational (b) Combinational Logic Logic Latch Latch Loops may borrow time internally but must complete within the cycle 10/2/18 VLSI-1 Class Notes Page 27 How Much Borrowing? 2-Phase Latches Tc tborrow £-( ttsetup+ nonoverlap ) 2 f1 f2 D1 Q1 D2 Q2 L1 Combinational Logic 1 L2 f 1 f t 2 nonoverlap Tc tsetup Tc/2 tborrow Nominal Half-Cycle 1 Delay D2 10/2/18 VLSI-1 Class Notes Page 28 Clock Skew § We have assumed zero clock skew § Clocks really have uncertainty in arrival time – Decreases maximum propagation delay – Increases minimum contamination delay – Decreases time borrowing 10/2/18 VLSI-1 Class Notes Page 29 Clock Skew: Flip-Flops clk clk Q1 D2 F1 Combinational Logic F2 Tc T ≥ t + (tpcq + tsetup + tskew) c pd clk tpcq tskew sequencing overhead t Q1 tpdq setup D2 clk tcd ≥ thold - tccq + tskew Q1 F1 CL clk D2 F2 tskew clk thold Q1 tccq D2 tcd 10/2/18 VLSI-1 Class Notes Page 30 Clock Skew: Latches 2-Phase Latches tpd ≤ Tc - (2tpdq) sequencing overhead t , t ≥ t - t - t + t cd1 cd2 hold ccq nonoverlap skew f1 f2 f1 D1 Q1 Combinational D2 Q2 Combinational D3 Q3 L1 L2 L3 tborrow ≤ Tc/2 - (tsetup + tnonoverlap + tskew) Logic 1 Logic 2 f 1 Pulsed Latches f 2 tpd ≤ Tc - max(tpdq, tpcq + tsetup - tpw + tskew ) sequencing overhead tcd ≥ thold + tpw - tccq + tskew tborrow ≤ Tpw - (tsetup + tskew) 10/2/18 VLSI-1 Class Notes 31 Clocking realities § If setup times are violated, reduce clock speed § Useful clock skew can be your friend § Jitter is NEVER your friend § Pulse latches do not scale well from generation to generation – Use them if you want lot’s of debugging experience J § Metastability is very real (and deadly) § Lastly, if hold times are violated, chip fails at any speed and PVT – You have a “brick” for a chip – You may be out of business if you are a startup 10/2/18 VLSI-1 Class Notes Page 32 Metastability Courtesy Altera 10/2/18 VLSI-1 Class Notes Page 33 Metastability - MTBF § The C1 and C2 constants depend on the device process and operating conditions.