
Home Search Collections Journals About Contact us My IOPscience Fabrication of planar organic nanotransistors using low temperature thermal nanoimprint lithography for chemical sensor applications This content has been downloaded from IOPscience. Please scroll down to see the full text. 2010 Nanotechnology 21 075301 (http://iopscience.iop.org/0957-4484/21/7/075301) View the table of contents for this issue, or go to the journal homepage for more Download details: IP Address: 134.129.182.74 This content was downloaded on 24/09/2013 at 12:05 Please note that terms and conditions apply. IOP PUBLISHING NANOTECHNOLOGY Nanotechnology 21 (2010) 075301 (7pp) doi:10.1088/0957-4484/21/7/075301 Fabrication of planar organic nanotransistors using low temperature thermal nanoimprint lithography for chemical sensor applications J Kettle1,5, S Whitelegg1,AMSong1,DCWedge2, L Kotacka3, V Kolarik3,MBMadec4,SGYeates4 and M L Turner4 1 Microelectronics and Nanostructures Group, School of Electrical and Electronics Engineering, University of Manchester, Sackville Street, Manchester M60 1QD, UK 2 Manchester Interdisciplinary Biocentre, University of Manchester, 131 Princess Street, Manchester M1 7ND, UK 3 Optaglio, s.r.o., Rez 199, 250 68, Czech Republic 4 Organic Materials Innovation Centre (OMIC), School of Chemistry, University of Manchester, Oxford Road, Manchester M13 9PL, UK Received 13 November 2009 Published 18 January 2010 Online at stacks.iop.org/Nano/21/075301 Abstract A new fabrication process for the patterning of organic semiconductors at the nanoscale has been developed using low temperature thermal nanoimprint lithography and the details of this process are discussed. Novel planar nanotransistors have been fabricated and characterized from poly(3-hexylthiophene) (P3HT) and we demonstrate the feasibility of using such devices as highly sensitive chemical sensors. (Some figures in this article are in colour only in the electronic version) 1. Introduction being fabricated via NIL technology [8]. In this technique, the source and drain electrodes are patterned using NIL followed A key advantage of organic over inorganic semiconductors is by the chemical vapor deposition (CVD) of pentacene on top the ability to use low cost, large area printing technologies of the nanogap electrodes for the active layer. Similarly, such as roll-to-roll, with the potential of incorporating Zhang et al have demonstrated a novel UV-transfer embossing nanoimprint lithography (NIL) into the process chain. Organic technique, whereby electrode arrays were patterned, with an field effect transistors (OFETs) based on low cost solution- estimated 5 µm gap, onto a substrate, followed by spin-casting processable materials have yielded impressive improvements of P3HT [9]. Nanofeatures using micro-contact printing of in performance, with mobilities of up to 2.5 cm2 V−1 s−1 being poly(dimethylsiloxane) stamps has been demonstrated on large demonstrated [1, 2]. With conventional printing techniques, area, flexible substrates, though the yield and reproducibility the minimum feature size is currently limited to around 20 µm, of this technique remain an issue [10]. However, to the best which is suitable for most device geometries used in 3D-OFET of our knowledge no ‘direct’ patterning of the active organic fabrication but only allow quite low performance, particularly semiconductor layer for OFETs by NIL has been accomplished to date. Nanoimprint lithography is an important emerging in terms of operational speed [3, 4]. Recently, conventional technology and is not restricted to small areas, and roll-to- photolithography techniques have been modified to enable roll processing [11] and large area imprinting are achievable. patterning of organic semiconductors down to feature sizes Structures with sub-10 nm resolution have been reported in the of 1 µm[5–7], with OFETs having submicron geometries literature [12]. 5 Present address: Organic Materials Innovation Centre (OMIC), School of Recent work has developed a novel 2D device based on the Chemistry, University of Manchester, Oxford Road, Manchester M13 9PL, design of a self-switching diode (SSD) fabricated from atomic- UK. force microscope (AFM) nanolithography of P3HT or PQT- 0957-4484/10/075301+07$30.00 1 © 2010 IOP Publishing Ltd Printed in the UK Nanotechnology 21 (2010) 075301 J Kettle et al 12 [13]. The SSD is a planar device, based on a single-layered structure with ohmic contacts also formed within the plane of the semiconductor nanochannel [14]. This is in contrast to conventional multi-layered vertical diode structures that are either based on a p–n doping junction or a barrier structure. Recently, we have demonstrated that organic SSDs could be fabricated using NIL, which would enable higher throughput and greater reproducibility than what is achievable using AFM lithography [15]. Planar nanotransistors, commonly referred to as an in- Figure 1. Schematic diagram illustrating the low temperature plane gate (IPG) transistor, were first introduced in an nanoimprint lithography process utilized in this paper for fabricating IPG transistors. Stage (1) involves spin-coating the PMMA, P3HT AlGaAs/GaAs two-dimensional electron gas (2DEG) by and PBMA layers, (2) involves embossing at low temperature to Wieck et al [16, 17]. In contrast to conventional FETs, where produce a thickness contrast, while at stage (3) the insulating lines in the metal gate is placed on top of the channel and gate insulator, the P3HT are formed by argon milling through the residual PBMA IPG transistors have a layout with the source, drain, current layer and P3HT. Finally, we removed the PBMA material (4). channel and one or two gates lying in the same plane. IPG transistors can realize control of the electric field parallel to the substrate (commonly, this is an inorganic two-dimensional molecular weight 337 000; glass transition temperature (Tg) ◦ electron gas), which results in a strong potential confinement 13–35 C[23] purchased from Sigma-Aldrich) dissolved in in the 1D channel. This planar device architecture can be anisole (7.5 wt%), a thermoplastic for geometric patterning, utilized to avoid contact resistance problems found for 3D was spin-coated onto the substrate at 3 krpm for 2 min and ◦ OFETs with nanoscale channel lengths. IPG transistors and baked for 30 min at 80 C in order to evaporate the solvent. We similar devices have now been realized in several material tested a range of polymer/solvent combinations and observed systems including SiGe/Si [18], GaAs/AlGaAs [19], silicon- that the minimum decrease in final film conductivity was on-insulator [20], indium tin oxide [21] and diamond-based obtained using this formula. materials [22]. Additionally, IPG based on n-type and p-type Imprinting was done using an in-house manufactured channels have been realized on a single substrate [23]. hydraulic hand press. Heating is achieved using cartridge This paper aims to demonstrate that IPG transistors can heaters, connected to a Eurotherm 301 PID temperature be fabricated into organic semiconductors using regioregular controller with a K-series thermocouple. During imprinting, P3HT. We have developed a new approach to patterning both the mold and PBMA-coated substrates were heated to polymer semiconductors at the nanoscale, which is described 60 ◦C, which is above the glass transition temperature range in more detail. Furthermore, we demonstrate the suitability of PBMA, enabling the polymer to become rubbery. The of P3HT-based IPG transistors as highly sensitive chemical temperature is raised at an initial rate of 30 ◦Cmin−1.Prior detection sensors. to the compression of the substrate and shim, the temperature was held at 60 ◦C for 10 min, to ensure an even distribution of 2. Experimental details heat across the sample surface and metallic heating elements. The mold was then pressed into the PBMA resist using a force The device structure used in these studies is shown in the of 1 kN and held at this force for 10 min to create a thickness schematic diagram in figure 1. For the device, n++ Si contrast in the PBMA. The nanoimprint templates, used in substrates with a 300 nm dry oxide layer were prepared this work, were fabricated into a silicon master by Qudos Ltd, using conventional solvent cleaning techniques. Wafers were in the UK and replicated into nickel by 3-DAG AG. After supplied by Si-Mat GmbH from Germany. The root mean 10 min hold time under high force, the sample was cooled square (RMS) surface roughness of this material was measured to room temperature using rapid air cooling. The advantage at 1.1 nm over a 20 µm × 20 µm area after cleaning. of using this embossing system is that it is possible to cool A thin layer (∼8 nm) of polymethylmethacrylate (PMMA, the substrate and stamp to room temperature without releasing Aldrich, weight average molecular weight 950 000) was spin- the force. This was a concern when working with PBMA coated (0.5 wt% in anisole) onto the substrate to improve the thermoplastic, due to the low Tg and is discussed further in the morphology of the P3HT and reduce the pin-hole density. results section. The mold was then separated from the PBMA ◦ The PMMA layer was hard baked at 220 ◦C, enabling the resist after cooling to 20 C to ensure that the thickness contrast PMMA films to be resistant to dissolution by trichlorobenzene in the PBMA was preserved. The residual thin resist in the (TCB). The use of a hard-baked PMMA buffer layer has been compressed region was removed by anisotropic argon milling previously shown to improve device stability by Sun et al [24]. (25 W, 25 sccm, 20 mTorr). This process created isolating lines Regioregular P3HT (regioregular ratio >94%, weight in the P3HT film, separating the gate from the source and drain. average molecular weight 55 kDa) was purchased from Rieke Argon milling was preferred over the conventional oxygen (O2) Metals Inc., dissolved in TCB at a concentration of 2.5 wt%, plasma etching technique, due to fears that oxygen etching was spin-coated onto the PMMA-coated substrate at 3 krpm would heavily dope the P3HT, which would later inhibit device for 4 min and annealed in nitrogen for 1 h at 120 ◦C.
Details
-
File Typepdf
-
Upload Time-
-
Content LanguagesEnglish
-
Upload UserAnonymous/Not logged-in
-
File Pages8 Page
-
File Size-