Carnegie Mellon The Memory Hierarchy 15-213 / 18-213: Introduc2on to Computer Systems 10th Lecture, Sep. 29, 2011 Instructors: Dave O’Hallaron, Greg Ganger, and Greg Kesden 1 Carnegie Mellon Today Storage technologies and trends Locality of reference Caching in the memory hierarchy 2 Carnegie Mellon Random-Access Memory (RAM) Key features . RAM is tradi2onally packaged as a chip. Basic storage unit is normally a cell (one bit per cell). Mul2ple RAM chips form a memory. StaAc RAM (SRAM) . Each cell stores a bit with a four or six-transistor circuit. Retains value indefinitely, as long as it is kept powered. Relavely insensi2ve to electrical noise (EMI), radiaon, etc. Faster and more expensive than DRAM. Dynamic RAM (DRAM) . Each cell stores bit with a capacitor. One transistor is used for access . Value must be refreshed every 10-100 ms. More sensi2ve to disturbances (EMI, radiaon,…) than SRAM. Slower and cheaper than SRAM. 3 Carnegie Mellon SRAM vs DRAM Summary Trans. Access Needs Needs per bit time refresh? EDC? Cost Applications SRAM 4 or 6 1X No Maybe 100x Cache memories DRAM 1 10X Yes Yes 1X Main memories, frame buffers 4 Carnegie Mellon ConvenAonal DRAM OrganizaAon d x w DRAM: . dw total bits organized as d supercells of size w bits 16 x 8 DRAM chip cols 0 1 2 3 2 bits 0 / addr 1 rows Memory 2 supercell controller (to/from CPU) (2,1) 3 8 bits / data Internal row buffer 5 Carnegie Mellon Reading DRAM Supercell (2,1) 16 x 8 DRAM chip Cols 0 1 2 3 RAS = 2 2 / 0 addr 1 Rows Memory controller 2 8 3 / data Internal row buffer 6 Carnegie Mellon Reading DRAM Supercell (2,1) 16 x 8 DRAM chip Cols 0 1 2 3 CAS = 1 2 / 0 addr To CPU 1 Rows Memory controller 2 supercell 8 3 (2,1) / data supercell Internal row buffer (2,1) 7 Carnegie Mellon Memory Modules addr (row = i, col = j) : supercell (i,j) DRAM 0 64 MB memory module DRAM 7 consisting of eight 8Mx8 DRAMs bits bits bits bits bits bits bits bits 56-63 48-55 40-47 32-39 24-31 16-23 8-15 0-7 63 56 55 48 47 40 39 32 31 24 23 16 15 8 7 0 Memory controller 64-bit doubleword at main memory address A 64-bit doubleword 8 Carnegie Mellon Enhanced DRAMs Basic DRAM cell has not changed since its invenAon in 1966. Commercialized by Intel in 1970. DRAM cores with beRer interface logic and faster I/O : . Synchronous DRAM (SDRAM) . Uses a conven2onal clock signal instead of asynchronous control . Allows reuse of the row addresses (e.g., RAS, CAS, CAS, CAS) . Double data-rate synchronous DRAM (DDR SDRAM) . Double edge clocking sends two bits per cycle per pin . Different types dis2nguished by size of small prefetch buffer: – DDR (2 bits), DDR2 (4 bits), DDR4 (8 bits) . By 2010, standard for most server and desktop systems . Intel Core i7 supports only DDR3 SDRAM 9 Carnegie Mellon NonvolaAle Memories DRAM and SRAM are volaAle memories . Lose informaon if powered off. Nonvolale memories retain value even if powered off . Read-only memory (ROM): programmed during produc2on . Programmable ROM (PROM): can be programmed once . Eraseable PROM (EPROM): can be bulk erased (UV, X-Ray) . Electrically eraseable PROM (EEPROM): electronic erase capability . Flash memory: EEPROMs with par2al (sector) erase capability . Wears out aer about 100,000 erasings. Uses for NonvolaAle Memories . Firmware programs stored in a ROM (BIOS, controllers for disks, network cards, graphics accelerators, security subsystems,…) . Solid state disks (replace rotang disks in thumb drives, smart phones, mp3 players, tablets, laptops,…) . Disk caches 10 Carnegie Mellon Tradional Bus Structure Connecng CPU and Memory A bus is a collecon of parallel wires that carry address, data, and control signals. Buses are typically shared by mulple devices. CPU chip Register file ALU System bus Memory bus I/O Main Bus interface bridge memory 11 Carnegie Mellon Memory Read TransacAon (1) CPU places address A on the memory bus. Register file Load operation: movl A, %eax ALU %eax Main memory I/O bridge 0 A Bus interface x A 12 Carnegie Mellon Memory Read TransacAon (2) Main memory reads A from the memory bus, retrieves word x, and places it on the bus. Register file Load operation: movl A, %eax ALU %eax Main memory I/O bridge x 0 Bus interface x A 13 Carnegie Mellon Memory Read TransacAon (3) CPU read word x from the bus and copies it into register %eax. Register file Load operation: movl A, %eax ALU %eax x Main memory I/O bridge 0 Bus interface x A 14 Carnegie Mellon Memory Write TransacAon (1) CPU places address A on bus. Main memory reads it and waits for the corresponding data word to arrive. Register file Store operation: movl %eax, A ALU %eax y Main memory I/O bridge 0 A Bus interface A 15 Carnegie Mellon Memory Write TransacAon (2) CPU places data word y on the bus. Register file Store operation: movl %eax, A ALU %eax y Main memory 0 I/O bridge y Bus interface A 16 Carnegie Mellon Memory Write TransacAon (3) Main memory reads data word y from the bus and stores it at address A. register file Store operation: movl %eax, A ALU %eax y main memory I/O bridge 0 bus interface y A 17 Carnegie Mellon What’s Inside A Disk Drive? Spindle Arm Platters Actuator Electronics (including a processor SCSI and memory!) connector Image courtesy of Seagate Technology 18 Carnegie Mellon Disk Geometry Disks consist of plaers, each with two surfaces. Each surface consists of concentric rings called tracks. Each track consists of sectors separated by gaps. Tracks Surface Track k Gaps Spindle Sectors 19 Carnegie Mellon Disk Geometry (Muliple-PlaRer View) Aligned tracks form a cylinder. Cylinder k Surface 0 Platter 0 Surface 1 Surface 2 Platter 1 Surface 3 Surface 4 Platter 2 Surface 5 Spindle 20 Carnegie Mellon Disk Capacity Capacity: maximum number of bits that can be stored. Vendors express capacity in units of gigabytes (GB), where 1 GB = 109 Bytes (Lawsuit pending! Claims decep2ve adver2sing). Capacity is determined by these technology factors: . Recording density (bits/in): number of bits that can be squeezed into a 1 inch segment of a track. Track density (tracks/in): number of tracks that can be squeezed into a 1 inch radial segment. Areal density (bits/in2): product of recording and track density. Modern disks parAAon tracks into disjoint subsets called recording zones . Each track in a zone has the same number of sectors, determined by the circumference of innermost track. Each zone has a different number of sectors/track 21 Carnegie Mellon CompuAng Disk Capacity Capacity = (# bytes/sector) x (avg. # sectors/track) x (# tracks/surface) x (# surfaces/plaRer) x (# plaRers/disk) Example: . 512 bytes/sector . 300 sectors/track (on average) . 20,000 tracks/surface . 2 surfaces/plaer . 5 plaers/disk Capacity = 512 x 300 x 20000 x 2 x 5 = 30,720,000,000 = 30.72 GB 22 Carnegie Mellon Disk OperaAon (Single-PlaRer View) The disk surface spins at a fixed The read/write head rotational rate is attached to the end of the arm and flies over the disk surface on a thin cushion of air. spindle spindle spindle spindle By moving radially, the arm can position the read/write head over any track. 23 Carnegie Mellon Disk OperaAon (MulA-PlaRer View) Read/write heads move in unison from cylinder to cylinder Arm Spindle 24 Carnegie Mellon Disk Structure - top view of single plaRer Surface organized into tracks Tracks divided into sectors 25 Carnegie Mellon Disk Access Head in position above a track 26 Carnegie Mellon Disk Access Rotation is counter-clockwise 27 Carnegie Mellon Disk Access – Read About to read blue sector 28 Carnegie Mellon Disk Access – Read After BLUE read After reading blue sector 29 Carnegie Mellon Disk Access – Read After BLUE read Red request scheduled next 30 Carnegie Mellon Disk Access – Seek After BLUE read Seek for RED Seek to red’s track 31 Carnegie Mellon Disk Access – RotaAonal Latency After BLUE read Seek for RED Rotational latency Wait for red sector to rotate around 32 Carnegie Mellon Disk Access – Read After BLUE read Seek for RED Rotational latency After RED read Complete read of red 33 Carnegie Mellon Disk Access – Service Time Components After BLUE read Seek for RED Rotational latency After RED read Data transfer Seek RotaAonal Data transfer latency 34 Carnegie Mellon Disk Access Time Average Ame to access some target sector approximated by : . Taccess = Tavg seek + Tavg rotaon + Tavg transfer Seek Ame (Tavg seek) . Time to posi2on heads over cylinder containing target sector. Typical Tavg seek is 3—9 ms RotaAonal latency (Tavg rotaon) . Time wai2ng for first bit of target sector to pass under r/w head. Tavg rotaon = 1/2 x 1/RPMs x 60 sec/1 min . Typical Tavg rotaon = 7200 RPMs Transfer me (Tavg transfer) . Time to read the bits in the target sector. Tavg transfer = 1/RPM x 1/(avg # sectors/track) x 60 secs/1 min. 35 Carnegie Mellon Disk Access Time Example Given: . Rotaonal rate = 7,200 RPM . Average seek 2me = 9 ms. Avg # sectors/track = 400. Derived: . Tavg rotaon = 1/2 x (60 secs/7200 RPM) x 1000 ms/sec = 4 ms. Tavg transfer = 60/7200 RPM x 1/400 secs/track x 1000 ms/sec = 0.02 ms . Taccess = 9 ms + 4 ms + 0.02 ms Important points: . Access 2me dominated by seek 2me and rotaonal latency. First bit in a sector is the most expensive, the rest are free.