IDT/sim IDT79S901 SYSTEM INTEGRATION MANAGER ROMABLE DEBUGGING KERNEL Integrated Device Technology, Inc. FEATURES Powerful Tool for Integration of RISController • Complete source code provided Based systems • Robust debug monitor • Supports remote source-level debug The IDT79S901 System Integration Manager (IDT/sim) is a GDB—IDT/c tool chain ROMable debug monitor product that permits convenient control and debug of RISC systems built around IDT's R30xx DBX—MIPS tool chain • Remote file access—connects target to remote host file RISController , R4400 , R4600 , R4700 and R4650 system CPUs. Facilities are included to operate the CPU under • Ethernet and Centronics support for fast download controlled conditions: examining and altering the contents of • Diagnostic tests for memory, cache, MMU, FPA, and memory, manipulating and controlling R30xx, R4xxx resources system (such as cache, TLB and coprocessors), loading programs • Adaptable to systems with or without hardware floating from host machines, and controlling the path of execution of point accelerator loaded programs. • Includes a variety of device drivers IDT/sim source code includes IDT's MicroMonitor, a very • Easy to add new user interface commands and I/O device simple monitor which requires only a UART and ROM to be drivers functional for performing the initial debugging and integration of new hardware. RS232C CABLE (DOWNLOAD & REMOTE DEBUG) TERMINAL SYSTEM UNDER DEVELOPMENT HOST SYSTEM TARGET WITH IDT/sim in EPROMs ( Sun 4, PC-DOS, or MIPS RISC/os) System Integration Manager 2867 drw 01 The IDT logo is a registered trademark, and IDT/c, IDT/sim, R3041, R3051, R3052, R3081, R4400, R4600, RISController, and RISCore are trademarks of Integrated Device Technology, Inc. SEPTEMBER 1995 1995 Integrated Device Technology, Inc. 7.9 DSC-9044/4 1 IDT79S901 IDT/sim SYSTEM INTEGRATION MANAGER PRODUCT BRIEF IDT/sim Features (source-level debug with gdb on and IDT/c Host or dbx on a MIPS RISC/os system; and Communications (remote file IDT/sim is a software tool to help system designers debug access, terminal emulator and set baud rate). hardware designs and port software to systems based on one of the R3000 ISA CPUs, R4400, R4600, R4700 and R4650. Run-Time Support The software is supplied in EPROMs on most IDT RISC Development products, and may be purchased in source- IDT/sim includes over 50 functions that can be called by user's code form so it can be modified, compiled and installed on programs to perform common I/O and R30xx, R4xxx control your system. operations. A complete list of commands is listed later in this document. IDT/sim provides all the basic functions needed to get a new hardware design debugged and to port and debug software on Feature Set it. Typically, the monitor is compiled and burned into EPROMs R4650 Orion Support: IDT/sim has been upgraded to sup- that are plugged into the target system. Approximately 115KB port the latest 64-bit RISController family member, the of EPROM is needed for the binary code, and 71KB of RAM 79R4650. This support has been implemented as a series of is needed for storing variables. Once installed, the designer "IFDEF" options to the base 32-bit source tree. This approach communicates with the monitor via a simple terminal con- allows a common set of features across 32 and 64-bit targets nected to an RS-232 port on the target system. Source code with a single development environment. is included to support a variety of UARTs for this port. On start- up, the monitor will determine the cache and main memory R3710/15 Support: IDT/sim now supports IDT79R3710/15 sizes automatically. Laser printer integrated system controller for IDT R30xx RISController family. Features supported are: ROM control- Diagnostics ler, DRAM controller, Centronics, Timer, Printer interface The monitor includes a set of diagnostic routines for testing the diagnostics. integrity of the hardware. The diagnostic suite includes: main IDT MicroMonitor: IDT/sim includes IDT's MicroMonitor, a memory tests which exercise all address and data paths; a very simple monitor for performing the initial debugging of new cache memory test which runs memory tests on both caches, hardware. checks tag memory, and verifies that instructions can be executed from cache; a system test which checks the ability Source-level Debug: Fully integrated with IDT's new com- to read and write full words, half-words, and bytes and checks piler toolchain (IDT/c Version 5.1) which supports source- the cache operation for valid, hit/miss, and invalidation; a level debug using gdb. IDT/sim supports gdb as a front end MMU test which checks the operation of the TLB inside the (with full access to /sim's commands) or use of an ASCII CPU; and a Floating Point test which tests the functionality of terminal in a stand-alone mode. the on-chip FPA, including exception interrupts. Remote File Access: IDT/sim has implemented features to Download Support allow connection of the target with a remote host file system allowing file transfer between target and host at run time. As Object code created on a software development system can an example, this can be useful for accessing large data be downloaded in either ASCII S-records or binary formats to images residing on a host without linking them with the the target system's memory. The code can be produced with application.Ethernet support is also included. IDT/c, the MIPS RISCross Compiler tools, or several third party compiler toolchains. Trace Facility: Traces the memory accesses of a user program. Provides for tracing the path of execution, reads- The IDT/sim console may also be used as a terminal to a from memory, or writes-to memory. Trace qualifiers allow the software development system accessed through a second tracing of a specific instruction or class of instructions or serial port. On targets which implement ethernet, utilities are references to particular memory ranges. The user may stop also available to support ethernet downloads, and remote file tracing on the following conditions: trace buffer full, hitting a access. breakpoint, executing a specific instruction, or accessing a specific memory range. The trace buffer contents may be Debug Commands displayed using standard R30xx, and R4xxx family mnemon- A variety of commands are included in IDT/sim to support ics. software/hardware debug. IDT/sim commands can be grouped into several categories, including: Execution Control (breakpoint, call, continue, go, gotill, next, step, unbreak); Memory Commands (assemble, cache flush, compare, disas- semble, dump, dump cache, dump registers, fill, fill registers, move read/write cache, search and substitute); TLB Com- mands (dump, flush, map, pid and probe); Remote Debug 7.9 2 IDT79S901 IDT/sim SYSTEM INTEGRATION MANAGER PRODUCT BRIEF KSEG 1 Unmapped, Uncached Physical Address Virtual Address 1fffffff bfffffff 1fc1ffff bfc1ffff EPROM SPACE 1fc00000 bfc00000 USER CODE SPACE a0011400 IDT/sim Stack 00011400 a0011400 a000f400 IDT/sim a0000100 Uninitialized RAM Data Area SPACE (bss) 00000000 a0000000 Int. Vectors a0000000 2867 drw 02 Figure 2 IDT/sim Memory Map Figure 2 shows the memory utilized by IDT/sim. The space, and is normally placed in 128KB of EPROM. IDT/sim EPROM space starts at virtual address bfc00000, which is the uses main memory to store interrupt vectors, variables, and a R3000's start-up address. The compiled version of IDT/sim stack. Approximately 71KB of RAM space is reserved for this with all features included occupies about 115KB of EPROM data. 7.9 3 IDT79S901 IDT/sim SYSTEM INTEGRATION MANAGER PRODUCT BRIEF IDT/sim COMMANDS asm <addr> examine and change memory interactively load|l [options] DEV using standard assembler mnemonics Download code to target benchmark/bm move|m [-w|-b|-h] <RANGE> <destination> Facilitates benchmarking Move the block of memory specified by RANGE to brk|b [addresslist] the address specified by destination Set/display breakpoints next/n [count] cacheflush/cf [-i|-d] Step over subroutine calls Flush the I-cache and/or the D-cache rad [-o|-d|-h] call|ca <address> [arg1 arg2 ... arg8} Set the default radix to the requested base. Call subroutine with up-to 8 arguments rc [-i] <-w|-b|-h] <RANGE> checksum|cs Isolate and read from cache Display the checksums for an address range regsel|rs [-c|-h] compare|cp [-w|-b|-h] <RANGE> <destination> Select either the compiler names or the hardware Compare the block of memory specified by RANGE names for registers to the block of memory that starts at destination search|sr [-w|-b|-h] <RANGE> <value> [mask] cont|c Search area of memory for value. Continues execution of the client process from seg [-0|-1|-2|-u] where it last halted execution. Set the default segment to the requested k-segment. dbgint|di [<-e|-d DEV>] setbaud/sb DEV Debug interrupt enable/disable - allows ‘break key’ Set the baud rate on a serial channel to generate external interrupt step|s [<count>] debug|db [DEV] Single step count times Enter remote debug mode sub [-w|-h|-b|-l|-r] <address> dis <RANGE> Examine and change memory interactively. Disassemble target memory specified by RANGE t {-a/-o/-e/-d/-r RANGE/-w RANGE/-c RANGE/-i INS/-m disptag|dt [-i] RANGE MSK} Displays the instruction or data cache tag values and Trace command data contents tc [-e BPNUM] [-d BPNUM] dr [reg#|name\reg_group] Trace conditionally command Print out the current contents of register(s) te [DEV] dt Connects the console port straight though to a Dump the trace buffer second serial port dump|d [-w|-h] <RANGE> tex [RANGE] Dump the