University of Massachusetts Amherst ScholarWorks@UMass Amherst Masters Theses 1911 - February 2014 2009 Application Specific uC stomization and Scalability of Soft ultM iprocessors Deepak C. Unnikrishnan University of Massachusetts Amherst Follow this and additional works at: https://scholarworks.umass.edu/theses Part of the Computer and Systems Architecture Commons, Digital Circuits Commons, Hardware Systems Commons, and the VLSI and Circuits, Embedded and Hardware Systems Commons Unnikrishnan, Deepak C., "Application Specific usC tomization and Scalability of Soft ultM iprocessors" (2009). Masters Theses 1911 - February 2014. 274. Retrieved from https://scholarworks.umass.edu/theses/274 This thesis is brought to you for free and open access by ScholarWorks@UMass Amherst. It has been accepted for inclusion in Masters Theses 1911 - February 2014 by an authorized administrator of ScholarWorks@UMass Amherst. For more information, please contact [email protected]. APPLICATION-SPECIFIC CUSTOMIZATION AND SCALABILITY OF SOFT MULTIPROCESSORS A Thesis Presented by DEEPAK C. UNNIKRISHNAN Submitted to the Graduate School of the University of Massachusetts Amherst in partial fulfillment of the requirements for the degree of MASTER OF SCIENCE May 2009 ELECTRICAL AND COMPUTER ENGINEERING © Copyright by Deepak C. Unnikrishnan 2009 All Rights Reserved APPLICATION-SPECIFIC CUSTOMIZATION AND SCALABILITY OF SOFT MULTIPROCESSORS A Thesis Presented by DEEPAK C. UNNIKRISHNAN Approved as to style and content by: _______________________________________ Russell G. Tessier, Chair _______________________________________ C. Mani Krishna, Member _______________________________________ Paul Siqueira, Member ____________________________________ C. V. Hollot, Department Head Electrical and Computer Engineering ACKNOWLEDGMENTS I would first like to thank Altera Corporation and the National Science Foundation for funding this project and allowing me to work on it. I would like to thank Professor Russell Tessier for his motivation and guidance. I am also grateful to Professor Mani Krishna and Professor Paul Siqueira for their time and for being on my thesis committee. I would like to extend my gratitude to Jia Zhao and Ramakrishna Vadlamani of the Reconfigurable Computing Group, UMass, for their valuable suggestions on the project. Finally, I would like to thank my friends and family who have assisted me and who have supported me throughout my time here at UMass. iv ABSTRACT APPLICATION-SPECIFIC CUSTOMIZATION AND SCALABILITY OF SOFT MULTIPROCESSORS MAY 2009 DEEPAK C. UNNIKRISHNAN B.TECH E.C.E (Hons.), UNIVERSITY OF CALICUT, INDIA M.S. E.C.E., UNIVERSITY OF MASSACHUSETTS, AMHERST Directed by: Professor Russell G. Tessier Soft multiprocessor systems exploit the plentiful computational resources available in field programmable devices. By virtue of their adaptability and ability to support coarse grained parallelism, they serve as excellent platforms for rapid prototyping and design space exploration of embedded multiprocessor applications. As complex applications emerge, careful mapping, processor and interconnect customization are critical to the overall performance of the multiprocessor system. In this thesis, we have developed an automated scalable framework to efficiently map applications written in a high-level programmer-friendly language to customizable soft-cores. The framework allows the user to specify the application in a high-level language called Streamit. After an initial analysis of the application, a soft multiprocessor system is generated automatically using a set of customizable SPREE processors which communicate with each other over point- to-point FIFO connections. Several micro-architectural features of the processors are then automatically customized on a per-application basis to improve system area, performance and power consumption. The efficiency and scalability of this approach has been validated using a diverse set of eight audio, video and signal processing benchmarks on v soft multiprocessor systems consisting of one to sixteen processors. Results show that generated soft multiprocessor systems consisting of sixteen processors can offer up to 6x speedup over a conventional single processor system. Our experiments with soft multiprocessor interconnection networks show that point-to-point topologies perform approximately 2x better than mesh topologies. Finally, we demonstrate that application- specific customizations on the instruction set, memory size, and inter-processor buffer size can improve the area and performance of the generated soft multiprocessor systems. The developed framework facilitates rapid design space exploration of soft multiprocessors. vi TABLE OF CONTENTS Page ACKNOWLEDGMENTS ................................................................................................. iv ABSTRACT.........................................................................................................................v LIST OF TABLES............................................................................................................. ix LIST OF FIGURES ............................................................................................................ x CHAPTER 1. INTRODUCTION ...........................................................................................................1 2. BACKGROUND AND PREVIOUS WORK..................................................................5 2.1 Soft Multiprocessor Synthesis ...........................................................................5 2.2 FPGA-Based Networks-On-Chip ......................................................................8 2.3 Soft Processor Optimization ............................................................................10 2.4 Summary of Previous Approaches...................................................................15 3. FRAMEWORK COMPONENTS .................................................................................18 3.1 Streamit – A compiler for stream-based applications......................................18 3.1.1 Streamit Language Constructs ..........................................................20 3.1.2 Streamit Compiler.............................................................................23 3.2 Automatic Soft Processor Generation..............................................................25 3.2.1 Soft Multiprocessor Interfaces..........................................................28 3.2.2 Interconnection Topologies ..............................................................31 3.2.3 Application Specific Soft Multiprocessor Optimizations.................35 vii 4. DESIGN FLOW.............................................................................................................39 5. EXPERIMENTAL RESULTS.......................................................................................44 5.1 Benchmarks......................................................................................................45 5.2 Interconnection topology variation..................................................................46 5.3 Customization of pipeline depth ......................................................................49 5.4 Customization of communication buffer depth ...............................................51 5.5 Soft multiprocessor ISA subsetting and memory size optimization................52 5.6 Application scalability .....................................................................................56 5.7 Combined impact of customizations................................................................59 6. SUMMARY AND FUTURE WORK ...........................................................................62 BIBLIOGRAPHY..............................................................................................................64 viii LIST OF TABLES Table Page Table 1: Resource usage of a simple FIFO............................................................... 30 Table 2: Framework Evaluation Benchmarks........................................................... 45 Table 3: Comparison of clock cycles and frequencies.............................................. 47 Table 4: Design frequency improvement by instruction subsetting ......................... 54 Table 5: Clock cycles and Frequency for 8 applications .......................................... 58 ix LIST OF FIGURES Figure Figure 1: Multiprocessor design for IPv4 after automated exploration ..................... 6 Figure 2: ESPAM Application Mapping Flow [4] ..................................................... 8 Figure 3: Topologies - A-Ring, B-Star, C-Mesh, D-Hypercube, E-Fully connected, F-Torus [5].................................................................................... 9 Figure 4: Overview of the SPREE System [11]........................................................ 11 Figure 5: A methodology to derive application specific embedded cores[12] ......... 12 Figure 6: CUSTARD –Tool flow and microarchitecture [13].................................. 14 Figure 7: Die Photograph of the RAW Microprocessor [19] ................................... 19 Figure 8: RAW fabric exposes on-chip interconnects to the software [19].............. 20 Figure 9: Stream structures supported by StreamIt [18]........................................... 21 Figure 10: FM Radio–Streamit progam and the equivalent stream graph [18] ........ 23 Figure 11: Streamit Compiler Phases [18]...............................................................