JTAG Debugger Technical Information Technical JTAG Debugger ■ Support for a wide range of on-chip debug interfaces ■ Easy high-level and assembler debugging ■ Interface to all compilers ■ Fast download ■ RTOS awareness ■ Interface to all hosts ■ Display of internal and external peripherals at a logical level ■ Flash programming ■ Hardware breakpoints and trigger (if supported by chip) ■ Trace extension available ■ Multiprocessor/multicore debugging ■ Software trace ■ Virtual analyzer ■ USB, Ethernet or Parallel Interface The Lauterbach product TRACE32-ICD supports a wide range of on-chip debug interfaces. The hardware for the debugger is universal and allows to interface different tar- get processors by simply changing the debug cable and the software. JTAG Debugger JTAG 05.12.10 TRACE32 - Technical Information 2 System Architecture Introduction The TRACE32 In-Circuit Debuggers The ICD-Debugger are mainly used as are highly cost effective tools for stand-alone debugger on a PC or work- debugging on assembler or HLL level. station. But they are also offered as an extension to the In-Circuit Emulator TRACE32-ICD Standard Host Host (Power) (PC or Workstation) Interface Debug Module Debug cable Debug connector Target Host Interfaces (Power) Debug Module ❏ LPT Universal debugger hardware for all architectures ❏ ISA Card CPU specific Debug Cable ❏ Ethernet JTAG Debugger System Architecture TRACE32 - Technical Information 3 TRACE32-ICD PowerDebug Power Host Debug (PC or Workstation) Module Debug cable Debug connector Target Power Debug Module CPU specific Debug Cable Universal debugger hardware for all architectures. Ethernet or USB inter- face included Multiprocessor Debugging A maximum of 4 debuggers can be connected to a host interface to config- Start/stop synchronization ure a multiprocessor development envi- ronment. It is of course also possible to If several processors are to be started use 2 debuggers and 2 trace modules. and stopped simultaneously as far as What hardware is controlled by which possible it is necessary to define which TRACE32 software component is functions as master and which as slave defined via a configuration file. in the overall configuration. The system can also be set so that all processors double as master and slave so when any processor is started all other pro- cessors are started and when any pro- JTAG Debugger System Architecture TRACE32 - Technical Information 4 cessor is stopped all others are must have a trigger input and a trigger stopped. A synchronous start can be output. If this is not the case, asynchro- carried out within about 10µs. Synchro- nous stopping must be implemented by nous stopping, for example at a break- software means which takes corre- point can be implemented exactly. As a spondingly longer. basic requirement for this, however, the debug interface of the processor used Host Host Debug Debug Debug (PC or Workstation) Interface Module Module Module Debug connector 1 Debug connector 2 Debug connector 3 Target JTAG Debugger System Architecture TRACE32 - Technical Information 5 Multicore Debugging The term multicore debugging is If more then one core are to be tested applied to the testing of multiple cores simultaneously several debug modules on a chip. are needed as in case of multiproces- If there are several cores integrated on sor debugging. There must be several a chip and each core has its own debug connectors with the same JTAG debug interface the same hardware signals on the target system. Alterna- and software configuration can be used tively, it is also possible to use an as for multiprocessor debugging. adapter that splits up the JTAG inter- face for several debuggers. It´s a different picture if all cores are driven via the same debug interface in Since several debugger now use the order to save pins. It is possible, for same debug port, steps must be taken example to daisy-chain several cores to ensure that only one debugger that run via the same debug port. This accesses the debug port at any time. is a popular solution at present for This can be automated by the debug chips with ARM cores since this task on the host controlling who has arrangement is very easy to implement exclusive access to the debug port with the JTAG interface. In this case the through the use of a semaphore sys- debugger requires the capability to tem. work with a specific core in the chain There are of course other configuration and to ensure that the control options for multiple cores in a chip sequences are passed through by the apart from daisy chaining. For more other cores. In the straightforward information on this topic contact our event that the developer only wants to technical support. work with a single core the position of the core in the chain can be set by soft- ware means. JTAG Debugger System Architecture TRACE32 - Technical Information 6 Software Concept Debugger Symbolic Debugging Local variables of the current function Stack frame to display function nesting Source listing in mixed mode A hierarchical symbol database addresses, module names and mem- enables structured symbolic debug- ory classes. The disassembler can use ging. Symbol names can be up to 255 the symbols for labels and/or oper- significant characters long and can be ands. Demangling for C++ signatures used to show single program is supported. JTAG Debugger Software Concept Debugger TRACE32 - Technical Information 7 High-Level Language Debugging TRACE32 can directly load the output struct both assembler and high-level of all standard compilers for C, C++, windows on the screen simulta- JAVA, Pascal, Modula2, PEARL and neously. All variable types specific to ADA from most compiler vendors. Pro- the high-level language can be dis- gram display and debugging can be played and modified. Addresses can be done in assembler, high-level or in a absolute, relative or line number based. mixture of both. It is possible to con- Debugging The debugger uses the following The onchip breakpoints can also be breakpoint implementations to stop the used to stop the program execution program execution at a certain instruc- after a read/write access to a specific tion: memory address. ❏ unlimited number of software The number of available onchip break- breakpoints for code in RAM points depends on the resources pro- ❏ a limited number of so-called vides by the CPU used. onchip breakpoints for code in ROM/FLASH JTAG Debugger Software Concept Debugger TRACE32 - Technical Information 8 Advanced breakpoints TRACE32-ICD provides also a simple way to set complex break conditions: ❏ Setting of breakpoints to the reading and writing of specific data values ❏ Linking the breakpoint with a condition ❏ Linking the breakpoint with commands that are executed whenever the breakpoint is reached ❏ Spot breakpoints on data accesses A combination of all 4 new features is also possible. RTOS Awareness The In-Circuit Debuggers provide dis- played. These functions are also avail- play functions, closely mirroring the able if the integral debugger is not command set of the integral debugger linked to the software. of the RTOS. The system resources e.g. tasks, objects, partitions, queues, regions and semaphores can be dis- Task list window and detailed window of one specific task JTAG Debugger Software Concept Debugger TRACE32 - Technical Information 9 Peripherals ❏ Display of onchip peripherals ❏ Pull down menues for settings ❏ User definable display of the ❏ Additional description for each onchip peripherals field ❏ Definition is done interactive ❏ supported by softkeys Flash Programming TRACE32 support the programming of of microcontrollers. The programming external flash memory as well as the can be controlled by the debugger or programming of internal flash memory by a routine in the target system. JTAG Debugger Software Concept Debugger TRACE32 - Technical Information 10 Software Trace If your TRACE32-ICD is not equipped formance measurements and time with a trace extension you can use the charting. A typical use of the software software trace feature to sample data trace is the trace and analysis of task and program information. switches. Here instead of the real trace memory A program flow trace is available for an array structure on the target is used architectures which provide a ´branch to store the trace data. Entries to this trace´ capability, like all PowerPC fami- array can be made by instrumenting lies and the SuperH SH4. the target program. The same trace display commands can be used for the software trace and the real trace memory. This includes per- TRACE32 Software Logger display commands Logger description block Software trace in target RAM JTAG Debugger Software Concept Debugger TRACE32 - Technical Information 11 Performance Analysis . Virtual Analyzer TRACE32-ICD provides the feature to To monitor selected data the virtual monitor changes in selected data over analyzer reads out the corresponding a period of time. As a basic require- memory cells in a fixed time pattern ment for this feature, the debug inter- during the program run and transfers face of the CPU used must support to their contents to its virtual trace mem- read the target memory while the pro- ory. Since the virtual trace is pure soft- gram is running. ware it can be of any size. Powerful Script Language The TRACE32 batch language the construction of command macros PRACTICE support automatic test, to expedite our development cycle. automatic system configurations and JTAG Debugger Software Concept Debugger TRACE32 - Technical Information 12 GUI Customization