© Copyright of Linköping University, all rights reserved ® TSEA80 by Dake Liu: [email protected] Design of Embedded DSP Processors Unit 7: Programming toolchain 9/26/2017 Unit 7 of TSEA26 – 2017 –H1 1 © Copyright of Linköping University, all rights reserved ® TSEA80 by Dake Liu: [email protected] Toolchain introduction There are two kinds of tools 1.The ASIP design tool for HW designers 。Frontend tool: Profiler and architecture optimizer 。Backend tool: Processor (ASIP) synthesizer 。Pipeline accurate simulator: For HW debugging 2.The assembly coding tool for programmers 。C-compiler, Assembler, Linker, (Loader) 。 Instruction set simulator: for ASM programmers 。 ASM coding Debugger: for firmware designers 9/26/2017 Unit 7 of TSEA26 – 2017 –H1 2 © Copyright of Linköping University, all rights reserved ® TSEA80 by Dake Liu: [email protected] Job loads to develop an ASIP Processor HW architecture Toolchain and kernel lib SW Ecological env 9/26/2017 Unit 7 of TSEA26 – 2017 –H1 3 Product © Copyright of Linköping University, all rights reserved ® Source code TSEA80 by Dake Liu: [email protected] Specification Lexical analysis, parsing Compiler Understand CFG extraction Front-end Applications CFG Front-end Function and Architecture design Static Specification Annotation profiling ASM Dynamic Instruction set Stimuli Critical path Specification profiling Cost and ASIP design Performance document Estimation ASIP Designer Synthesizer Idea + Application analysis Benchmark nML language, PDG language and chess compiler Synthesized ASIP Architecture Assembly Constraint Back-end description Instruction set description design Functional Verification Synopsys ASIP Designer generator Cost, ASIP Design Flow Design ASIP Performance and Power Estimation A generated ASIP (processor) VLSI Compiler Assembler Simulator RTL code Implementation exam not for Good to know, Traditional VLSI design Silicon Cost and Power Release © Copyright of Linköping① University, all rights reserved ® TSEA80 by Dake Liu: [email protected] Source code A Compiler front-end ⑦ Executable Using Lexical analysis Dyn analysis GCC Parsing Parse tree optimization ⑧ Stimuli Execute program ② Parse tree Static analysis ⑨ Branch taken % CFG extraction CFG ③ Profile analysis Basic block (bb) Annotation cost estimation ⑩ ASIP design document Annotated bb cost table ⑤ ④ parse tree GCC: GNU Compiler Collection Compiler back-end CFG: control flow graph GEM: GNU C Compiler Extensions Framework ⑥ Using Probe lib Code generation GCC Linking Available profiler: Relief 9/26/2017 ForGEM teachers using the book 5 A for application analysis © Copyright of Linköping University, all rights reserved ® TSEA80 by Dake Liu: [email protected] Synopsys ASIP Designer Specification Processor Model primitive nML PDG compiler header file file file header file Compiler Assembler Simulator RTL Linker Unit 7 of TSEA26 – 2017 –H1 © Copyright of Linköping University, all rights reserved ® TSEA80 by Dake Liu: [email protected] ASM coding tools 9/26/2017 Unit 7 of TSEA26 – 2017 –H1 7 © Copyright of Linköping University, all rights reserved ® TSEA80 by Dake Liu: [email protected] ASIP User's View on tools Behavior (C code) modeling (1) (2) (1) Source file editor (2) Function allocation to HW (1) (2) (3) Behavior simulator (3) HSA, HW-adapter Behavior code adapt to HW (1)(2) (3) Build assembly program library (4) C-compiler Compile C code to assembly (4) Assembly programming (5) (6) (7) (5) Assembler (6) Link objective codes and allocate codes to program memory (6) Objective linker Generate finally binary code and simulation using the binary code (7) (8) (7) ASM simulator Verify codes, benchmarking, profiling, and release the design (5) (6) (7) (8) (8) Debugger (a) The method translating source code to qualified assembly code (b) Toolchain 9/26/2017 Unit 7 of TSEA26 – 2017 –H1 8 © Copyright of Linköping University, all rights reserved ® TSEA80 by Dake Liu: [email protected] The focus in unit 7 today • Briefly introduce compiler, because there is another compiler course • Focus on Simulator – Cycle accurate (microarchitecture) simulator • For HW development and verifications – Instruction set (behavior) simulator ISS • For firmware implementation and debugging • Trace driven simulator: fast sim, no-exec high MI/S • Execution driven simulator: easy design for ASIP 9/26/2017 Unit 7 of TSEA26 – 2017 –H1 9 © Copyright of Linköping University, all rights reserved ® TSEA80 by Dake Liu: [email protected] What is a compiler • A compiler is a program that reads a program written in one language (usually a high-level language) and translates it into an equivalent program in another language (usually a low- level language) • For an ASIP programmer, the source language is C and the target language is ASM 9/26/2017 Unit 7 of TSEA26 – 2017 –H1 10 © Copyright of Linköping University, all rightsSource reserved program ® TSEA80 by Dake Liu: [email protected] String of characters Lexical analyzer String of tokens zer Parser Analy Parse tree Semantic analyzer Parse tree /AST Symbol-table manager Error handler Intermediate code generator Intermediate representation Code optimizer Intermediate representation Synthesizer Code generator Relocatable assembly code structure Compiler Target code optimizer Relocatable assembly code 9/26/2017 For teachers using the book 11 Target program © Copyright of Linköping University, all rights reserved ® TSEA80 by Dake Liu: [email protected] Compiler structure • Compilation consists of two phases: analysis and synthesis. – Analyzer: It breaks the source program into consecutive pieces and conducts lexical, syntactical, and semantic analysis. – Synthesizer: creates intermediate representation (IR) versus source program. IR Code is then optimized on IR level. Finally, ASM codes (glibc call) are selected based on the optimized IR code. 9/26/2017 Unit 7 of TSEA26 – 2017 –H1 12 © Copyright of Linköping University, all rights reserved ® TSEA80 by Dake Liu: [email protected] Frontend analyzer • Lexical analysis and parsing C program, early code filtering, and generate abstract syntax tree /control flow graph). 9/26/2017 Unit 7 of TSEA26 – 2017 –H1 13 © Copyright of Linköping University, all rights reserved ® TSEA80 by Dake Liu: [email protected] Code optimization • Most compiler researches are optimizations – So many papers can be found, such as…… – Data Flow Optimizations: identify and handling independent operations – Common sub-expression elimination: eliminate more expressions compute the same value – Loop Optimizations: minimize the inner-most loop runtime, M size, or memory access cost 9/26/2017 Unit 7 of TSEA26 – 2017 –H1 14 © Copyright of Linköping University, all rights reserved ® TSEA80 by Dake Liu: [email protected] Code generation • The final step in a compiler is target code generation and optimization – Instruction Selection: match IR operations to target template (in the template table) – Register Allocation: Allocate variables and generate load store instructions – Instruction Scheduling: improve instruction- level parallelism via pipeline 9/26/2017 Unit 7 of TSEA26 – 2017 –H1 15 © Copyright of Linköping University, all rights reserved ® TSEA80 by Dake Liu: [email protected] Assembler as a program • Assembler is a computer program – Translates assembly instruction mnemonics, memory locations, and other entities into binary machine code. – The input of an assembler is assembly code. – The output file is an object file, containing relocatable binary codes and bookkeeping information (symbol table for the linker). 9/26/2017 Unit 7 of TSEA26 – 2017 –H1 16 © Copyright of Linköping University, all rights reserved ® TSEA80 by Dake Liu: [email protected] Assembler design/construction • The translation consists of two steps. 1. Find memory locations with labels: by calculating addresses of all symbolic address names. 2. Translate each assembly statement, mnemonic, register, configuration switch, and label into binary code • Finally, the assembler produces an output file (object file), containing the machine instructions, data, and bookkeeping information. 9/26/2017 Unit 7 of TSEA26 – 2017 –H1 17 © Copyright of Linköping University, all rights reserved ® TSEA80 by Dake Liu: [email protected] Kernel part of Senior Assembler Load an assembly source file (*.ASM) Load initial symbol table (reserved mnemonics) 2nd pass 1st pass Get code from internal code list Read token from source (merge lexical and syntax analyses) Does code Is identification y n need identification / label defined in error Token in y y / label patching Redefinition error symbol table symbol table? of token n n n y Add token to symbol table n End of Patch code in code list with value Code list of identification / label y Add token to ASM expression 3rd pass y n n ASM expression ASM expression error complete syntax OK Find memory locations with labels: by calculating addresses of all symbolic address names y n End of Concatenate code to internal code source? Generate machine code and bookkeeping symbol table as the list output from internal code list y 9/26/2017 Unit 7 of TSEA26 – 2017 –H1 18 © Copyright of Linköping University, all rights reserved ® TSEA80 by Dake Liu: [email protected] Linker as a program • A linker is a program, it takes object modules with linking tables and library / subroutine codes as inputs, merges them, generates final (code and data) addresses, executable binary machine codes. • By separating assembler and linker, code can be re-locatable 9/26/2017 Unit 7 of TSEA26 – 2017 –H1 19 © Copyright of Linköping University, all rights reserved ® TSEA80 by